TY - GEN
T1 - DFT for achieving hybrid transiton delay fault test with reduced pin count testing
AU - Son, Changwon
AU - Ahn, Seongyong
AU - Kang, Sungho
PY - 2009
Y1 - 2009
N2 - This paper presents a new DFT (Design-for-Testability) for achieving the hybrid TDF (Transition Delay Fault) test with RPCT (Reduced Pin Count Testing). RPCT can perform stuck-at test only due to the limitation of boundary scan structure. With increasing of operating frequency, it is more important to perform at-speed tests and achieve higher TDF coverage. With our proposed design, it is possible to perform at-speed delay test in RPCT structure with little hardware overhead and higher test throughput. Experimental results for ISCAS89 and ITC99 benchmark circuits prove that the proposed design is effective for the test cost reduction by minimizing hardware overhead and maximizing multi-site test.
AB - This paper presents a new DFT (Design-for-Testability) for achieving the hybrid TDF (Transition Delay Fault) test with RPCT (Reduced Pin Count Testing). RPCT can perform stuck-at test only due to the limitation of boundary scan structure. With increasing of operating frequency, it is more important to perform at-speed tests and achieve higher TDF coverage. With our proposed design, it is possible to perform at-speed delay test in RPCT structure with little hardware overhead and higher test throughput. Experimental results for ISCAS89 and ITC99 benchmark circuits prove that the proposed design is effective for the test cost reduction by minimizing hardware overhead and maximizing multi-site test.
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U2 - 10.1109/SOCDC.2009.5423888
DO - 10.1109/SOCDC.2009.5423888
M3 - Conference contribution
AN - SCOPUS:77951436253
SN - 9781424450343
T3 - 2009 International SoC Design Conference, ISOCC 2009
SP - 128
EP - 132
BT - 2009 International SoC Design Conference, ISOCC 2009
T2 - 2009 International SoC Design Conference, ISOCC 2009
Y2 - 22 November 2009 through 24 November 2009
ER -