DFT for achieving hybrid transiton delay fault test with reduced pin count testing

Changwon Son, Seongyong Ahn, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a new DFT (Design-for-Testability) for achieving the hybrid TDF (Transition Delay Fault) test with RPCT (Reduced Pin Count Testing). RPCT can perform stuck-at test only due to the limitation of boundary scan structure. With increasing of operating frequency, it is more important to perform at-speed tests and achieve higher TDF coverage. With our proposed design, it is possible to perform at-speed delay test in RPCT structure with little hardware overhead and higher test throughput. Experimental results for ISCAS89 and ITC99 benchmark circuits prove that the proposed design is effective for the test cost reduction by minimizing hardware overhead and maximizing multi-site test.

Original languageEnglish
Title of host publication2009 International SoC Design Conference, ISOCC 2009
Pages128-132
Number of pages5
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of
Duration: 2009 Nov 222009 Nov 24

Other

Other2009 International SoC Design Conference, ISOCC 2009
CountryKorea, Republic of
CityBusan
Period09/11/2209/11/24

Fingerprint

Design for testability
Testing
Hardware
Cost reduction
Throughput
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Son, C., Ahn, S., & Kang, S. (2009). DFT for achieving hybrid transiton delay fault test with reduced pin count testing. In 2009 International SoC Design Conference, ISOCC 2009 (pp. 128-132). [5423888] https://doi.org/10.1109/SOCDC.2009.5423888
Son, Changwon ; Ahn, Seongyong ; Kang, Sungho. / DFT for achieving hybrid transiton delay fault test with reduced pin count testing. 2009 International SoC Design Conference, ISOCC 2009. 2009. pp. 128-132
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Son, C, Ahn, S & Kang, S 2009, DFT for achieving hybrid transiton delay fault test with reduced pin count testing. in 2009 International SoC Design Conference, ISOCC 2009., 5423888, pp. 128-132, 2009 International SoC Design Conference, ISOCC 2009, Busan, Korea, Republic of, 09/11/22. https://doi.org/10.1109/SOCDC.2009.5423888

DFT for achieving hybrid transiton delay fault test with reduced pin count testing. / Son, Changwon; Ahn, Seongyong; Kang, Sungho.

2009 International SoC Design Conference, ISOCC 2009. 2009. p. 128-132 5423888.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Son C, Ahn S, Kang S. DFT for achieving hybrid transiton delay fault test with reduced pin count testing. In 2009 International SoC Design Conference, ISOCC 2009. 2009. p. 128-132. 5423888 https://doi.org/10.1109/SOCDC.2009.5423888