DFT for achieving hybrid transiton delay fault test with reduced pin count testing

Changwon Son; Seongyong Ahn; Sungho Kang

doi:10.1109/SOCDC.2009.5423888

DFT for achieving hybrid transiton delay fault test with reduced pin count testing

Changwon Son, Seongyong Ahn, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a new DFT (Design-for-Testability) for achieving the hybrid TDF (Transition Delay Fault) test with RPCT (Reduced Pin Count Testing). RPCT can perform stuck-at test only due to the limitation of boundary scan structure. With increasing of operating frequency, it is more important to perform at-speed tests and achieve higher TDF coverage. With our proposed design, it is possible to perform at-speed delay test in RPCT structure with little hardware overhead and higher test throughput. Experimental results for ISCAS89 and ITC99 benchmark circuits prove that the proposed design is effective for the test cost reduction by minimizing hardware overhead and maximizing multi-site test.

Original language	English
Title of host publication	2009 International SoC Design Conference, ISOCC 2009
Pages	128-132
Number of pages	5
DOIs	https://doi.org/10.1109/SOCDC.2009.5423888
Publication status	Published - 2009 Dec 1
Event	2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of Duration: 2009 Nov 22 → 2009 Nov 24

Other

Other	2009 International SoC Design Conference, ISOCC 2009
Country	Korea, Republic of
City	Busan
Period	09/11/22 → 09/11/24

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/SOCDC.2009.5423888

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Son, C., Ahn, S., & Kang, S. (2009). DFT for achieving hybrid transiton delay fault test with reduced pin count testing. In 2009 International SoC Design Conference, ISOCC 2009 (pp. 128-132). [5423888] https://doi.org/10.1109/SOCDC.2009.5423888

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abstract = "This paper presents a new DFT (Design-for-Testability) for achieving the hybrid TDF (Transition Delay Fault) test with RPCT (Reduced Pin Count Testing). RPCT can perform stuck-at test only due to the limitation of boundary scan structure. With increasing of operating frequency, it is more important to perform at-speed tests and achieve higher TDF coverage. With our proposed design, it is possible to perform at-speed delay test in RPCT structure with little hardware overhead and higher test throughput. Experimental results for ISCAS89 and ITC99 benchmark circuits prove that the proposed design is effective for the test cost reduction by minimizing hardware overhead and maximizing multi-site test.",

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doi = "10.1109/SOCDC.2009.5423888",

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N2 - This paper presents a new DFT (Design-for-Testability) for achieving the hybrid TDF (Transition Delay Fault) test with RPCT (Reduced Pin Count Testing). RPCT can perform stuck-at test only due to the limitation of boundary scan structure. With increasing of operating frequency, it is more important to perform at-speed tests and achieve higher TDF coverage. With our proposed design, it is possible to perform at-speed delay test in RPCT structure with little hardware overhead and higher test throughput. Experimental results for ISCAS89 and ITC99 benchmark circuits prove that the proposed design is effective for the test cost reduction by minimizing hardware overhead and maximizing multi-site test.

AB - This paper presents a new DFT (Design-for-Testability) for achieving the hybrid TDF (Transition Delay Fault) test with RPCT (Reduced Pin Count Testing). RPCT can perform stuck-at test only due to the limitation of boundary scan structure. With increasing of operating frequency, it is more important to perform at-speed tests and achieve higher TDF coverage. With our proposed design, it is possible to perform at-speed delay test in RPCT structure with little hardware overhead and higher test throughput. Experimental results for ISCAS89 and ITC99 benchmark circuits prove that the proposed design is effective for the test cost reduction by minimizing hardware overhead and maximizing multi-site test.

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