DHL-cache: Dynamic per history length adjustment for low-power L2 cache

H. W. Joo; E. Y. Chung

doi:10.1049/el.2016.1465

DHL-cache: Dynamic per history length adjustment for low-power L2 cache

H. W. Joo, E. Y. Chung

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

The significant power dissipation of the on-chip L2 cache is a major concern in modern microprocessors. This Letter proposes a unique low-power technique for a high-associative large L2 cache that has fragmented locality by L1 cache. The dynamic per history length adjustment cache (DHL-cache) dynamically selects the qualified way candidates to be accessed and controls the way-prediction window size based on the access history pattern. With a high degree of the way-prediction accuracy, the DHL-cache shows a 55.3% energydelay product improvement over the location-cache with minimum hardware support. Therefore, the DHL-cache alleviates the power limit issue for L2 cache, even with high associativity and fragmented locality.

Original language	English
Pages (from-to)	1297-1298
Number of pages	2
Journal	Electronics Letters
Volume	52
Issue number	15
DOIs	https://doi.org/10.1049/el.2016.1465
Publication status	Published - 2016 Jul 21

Bibliographical note

Funding Information:
This work was supported by the ICT RandD program of MSIP/IITP [2016 (R7177-16-0233), Development of Application Program Optimization Tools for High Performance Computing Systems].

Publisher Copyright:
© 2016 The Institution of Engineering and Technology.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1049/el.2016.1465

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abstract = "The significant power dissipation of the on-chip L2 cache is a major concern in modern microprocessors. This Letter proposes a unique low-power technique for a high-associative large L2 cache that has fragmented locality by L1 cache. The dynamic per history length adjustment cache (DHL-cache) dynamically selects the qualified way candidates to be accessed and controls the way-prediction window size based on the access history pattern. With a high degree of the way-prediction accuracy, the DHL-cache shows a 55.3% energydelay product improvement over the location-cache with minimum hardware support. Therefore, the DHL-cache alleviates the power limit issue for L2 cache, even with high associativity and fragmented locality.",

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DHL-cache: Dynamic per history length adjustment for low-power L2 cache

Abstract

Bibliographical note

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