DHL-cache: Dynamic per history length adjustment for low-power L2 cache

H. W. Joo; E. Y. Chung

doi:10.1049/el.2016.1465

DHL-cache: Dynamic per history length adjustment for low-power L2 cache

H. W. Joo, E. Y. Chung

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

The significant power dissipation of the on-chip L2 cache is a major concern in modern microprocessors. This Letter proposes a unique low-power technique for a high-associative large L2 cache that has fragmented locality by L1 cache. The dynamic per history length adjustment cache (DHL-cache) dynamically selects the qualified way candidates to be accessed and controls the way-prediction window size based on the access history pattern. With a high degree of the way-prediction accuracy, the DHL-cache shows a 55.3% energydelay product improvement over the location-cache with minimum hardware support. Therefore, the DHL-cache alleviates the power limit issue for L2 cache, even with high associativity and fragmented locality.

Original language	English
Pages (from-to)	1297-1298
Number of pages	2
Journal	Electronics Letters
Volume	52
Issue number	15
DOIs	https://doi.org/10.1049/el.2016.1465
Publication status	Published - 2016 Jul 21

Bibliographical note

Funding Information:
This work was supported by the ICT RandD program of MSIP/IITP [2016 (R7177-16-0233), Development of Application Program Optimization Tools for High Performance Computing Systems].

Publisher Copyright:
© 2016 The Institution of Engineering and Technology.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1049/el.2016.1465

Cite this

@article{d951579e418a47f4880b308a99860f49,

title = "DHL-cache: Dynamic per history length adjustment for low-power L2 cache",

abstract = "The significant power dissipation of the on-chip L2 cache is a major concern in modern microprocessors. This Letter proposes a unique low-power technique for a high-associative large L2 cache that has fragmented locality by L1 cache. The dynamic per history length adjustment cache (DHL-cache) dynamically selects the qualified way candidates to be accessed and controls the way-prediction window size based on the access history pattern. With a high degree of the way-prediction accuracy, the DHL-cache shows a 55.3% energydelay product improvement over the location-cache with minimum hardware support. Therefore, the DHL-cache alleviates the power limit issue for L2 cache, even with high associativity and fragmented locality.",

author = "Joo, {H. W.} and Chung, {E. Y.}",

note = "Funding Information: This work was supported by the ICT RandD program of MSIP/IITP [2016 (R7177-16-0233), Development of Application Program Optimization Tools for High Performance Computing Systems]. Publisher Copyright: {\textcopyright} 2016 The Institution of Engineering and Technology.",

year = "2016",

month = jul,

day = "21",

doi = "10.1049/el.2016.1465",

language = "English",

volume = "52",

pages = "1297--1298",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "Institution of Engineering and Technology",

number = "15",

}

TY - JOUR

T1 - DHL-cache

T2 - Dynamic per history length adjustment for low-power L2 cache

AU - Joo, H. W.

AU - Chung, E. Y.

N1 - Funding Information: This work was supported by the ICT RandD program of MSIP/IITP [2016 (R7177-16-0233), Development of Application Program Optimization Tools for High Performance Computing Systems]. Publisher Copyright: © 2016 The Institution of Engineering and Technology.

PY - 2016/7/21

Y1 - 2016/7/21

N2 - The significant power dissipation of the on-chip L2 cache is a major concern in modern microprocessors. This Letter proposes a unique low-power technique for a high-associative large L2 cache that has fragmented locality by L1 cache. The dynamic per history length adjustment cache (DHL-cache) dynamically selects the qualified way candidates to be accessed and controls the way-prediction window size based on the access history pattern. With a high degree of the way-prediction accuracy, the DHL-cache shows a 55.3% energydelay product improvement over the location-cache with minimum hardware support. Therefore, the DHL-cache alleviates the power limit issue for L2 cache, even with high associativity and fragmented locality.

AB - The significant power dissipation of the on-chip L2 cache is a major concern in modern microprocessors. This Letter proposes a unique low-power technique for a high-associative large L2 cache that has fragmented locality by L1 cache. The dynamic per history length adjustment cache (DHL-cache) dynamically selects the qualified way candidates to be accessed and controls the way-prediction window size based on the access history pattern. With a high degree of the way-prediction accuracy, the DHL-cache shows a 55.3% energydelay product improvement over the location-cache with minimum hardware support. Therefore, the DHL-cache alleviates the power limit issue for L2 cache, even with high associativity and fragmented locality.

UR - http://www.scopus.com/inward/record.url?scp=84978758744&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84978758744&partnerID=8YFLogxK

U2 - 10.1049/el.2016.1465

DO - 10.1049/el.2016.1465

M3 - Article

AN - SCOPUS:84978758744

VL - 52

SP - 1297

EP - 1298

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 15

ER -

DHL-cache: Dynamic per history length adjustment for low-power L2 cache

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this