The significant power dissipation of the on-chip L2 cache is a major concern in modern microprocessors. This Letter proposes a unique low-power technique for a high-associative large L2 cache that has fragmented locality by L1 cache. The dynamic per history length adjustment cache (DHL-cache) dynamically selects the qualified way candidates to be accessed and controls the way-prediction window size based on the access history pattern. With a high degree of the way-prediction accuracy, the DHL-cache shows a 55.3% energydelay product improvement over the location-cache with minimum hardware support. Therefore, the DHL-cache alleviates the power limit issue for L2 cache, even with high associativity and fragmented locality.
Bibliographical noteFunding Information:
This work was supported by the ICT RandD program of MSIP/IITP [2016 (R7177-16-0233), Development of Application Program Optimization Tools for High Performance Computing Systems].
© 2016 The Institution of Engineering and Technology.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering