Diagnosis of Scan Chain Faults Based-on Machine-Learning

Hyeonchan Lim; Tae Hyun Kim; Seunghwan Kim; Sungho Kang

doi:10.1109/ISOCC50952.2020.9333074

Diagnosis of Scan Chain Faults Based-on Machine-Learning

Hyeonchan Lim, Tae Hyun Kim, Seunghwan Kim, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

In order to improve yield of nanometer-scale chips, scan-based test and diagnosis are important. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method based on two-stage neural networks is proposed for not only stuck-At fault but also transition fault. Experimental results on benchmark circuits show that the proposed method is 10% more accurate than a previous work and CPU time for training the neural networks is also reduced dramatically.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	57-58
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9333074
Publication status	Published - 2020 Oct 21
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 2020 Oct 21 → 2020 Oct 24

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country/Territory	Korea, Republic of
City	Yeosu
Period	20/10/21 → 20/10/24

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This work was supported by the MOTIE and KEIT [20012010, Design for Test of Intelligent Processors]

Publisher Copyright:
© 2020 IEEE.

All Science Journal Classification (ASJC) codes

Energy Engineering and Power Technology
Electrical and Electronic Engineering
Instrumentation
Artificial Intelligence
Hardware and Architecture

Access to Document

10.1109/ISOCC50952.2020.9333074

Cite this

@inproceedings{918daefb5d7e43d2a3ada2049e98e5fb,

title = "Diagnosis of Scan Chain Faults Based-on Machine-Learning",

abstract = "In order to improve yield of nanometer-scale chips, scan-based test and diagnosis are important. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method based on two-stage neural networks is proposed for not only stuck-At fault but also transition fault. Experimental results on benchmark circuits show that the proposed method is 10% more accurate than a previous work and CPU time for training the neural networks is also reduced dramatically.",

author = "Hyeonchan Lim and Kim, {Tae Hyun} and Seunghwan Kim and Sungho Kang",

note = "Funding Information: ACKNOWLEDGMENT This work was supported by the MOTIE and KEIT [20012010, Design for Test of Intelligent Processors] Publisher Copyright: {\textcopyright} 2020 IEEE.; 17th International System-on-Chip Design Conference, ISOCC 2020 ; Conference date: 21-10-2020 Through 24-10-2020",

year = "2020",

month = oct,

day = "21",

doi = "10.1109/ISOCC50952.2020.9333074",

language = "English",

series = "Proceedings - International SoC Design Conference, ISOCC 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "57--58",

booktitle = "Proceedings - International SoC Design Conference, ISOCC 2020",

address = "United States",

}

Lim, H, Kim, TH, Kim, S & Kang, S 2020, Diagnosis of Scan Chain Faults Based-on Machine-Learning. in Proceedings - International SoC Design Conference, ISOCC 2020., 9333074, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 57-58, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 20/10/21. https://doi.org/10.1109/ISOCC50952.2020.9333074

Diagnosis of Scan Chain Faults Based-on Machine-Learning. / Lim, Hyeonchan; Kim, Tae Hyun; Kim, Seunghwan et al.

Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 57-58 9333074 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Diagnosis of Scan Chain Faults Based-on Machine-Learning

AU - Lim, Hyeonchan

AU - Kim, Tae Hyun

AU - Kim, Seunghwan

AU - Kang, Sungho

PY - 2020/10/21

Y1 - 2020/10/21

N2 - In order to improve yield of nanometer-scale chips, scan-based test and diagnosis are important. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method based on two-stage neural networks is proposed for not only stuck-At fault but also transition fault. Experimental results on benchmark circuits show that the proposed method is 10% more accurate than a previous work and CPU time for training the neural networks is also reduced dramatically.

AB - In order to improve yield of nanometer-scale chips, scan-based test and diagnosis are important. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method based on two-stage neural networks is proposed for not only stuck-At fault but also transition fault. Experimental results on benchmark circuits show that the proposed method is 10% more accurate than a previous work and CPU time for training the neural networks is also reduced dramatically.

UR - http://www.scopus.com/inward/record.url?scp=85100798301&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85100798301&partnerID=8YFLogxK

U2 - 10.1109/ISOCC50952.2020.9333074

DO - 10.1109/ISOCC50952.2020.9333074

M3 - Conference contribution

AN - SCOPUS:85100798301

T3 - Proceedings - International SoC Design Conference, ISOCC 2020

SP - 57

EP - 58

BT - Proceedings - International SoC Design Conference, ISOCC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 17th International System-on-Chip Design Conference, ISOCC 2020

Y2 - 21 October 2020 through 24 October 2020

ER -

Diagnosis of Scan Chain Faults Based-on Machine-Learning

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this