Diagnosis of Scan Chain Faults Based-on Machine-Learning

Hyeonchan Lim, Tae Hyun Kim, Seunghwan Kim, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)


In order to improve yield of nanometer-scale chips, scan-based test and diagnosis are important. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method based on two-stage neural networks is proposed for not only stuck-At fault but also transition fault. Experimental results on benchmark circuits show that the proposed method is 10% more accurate than a previous work and CPU time for training the neural networks is also reduced dramatically.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference, ISOCC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)9781728183312
Publication statusPublished - 2020 Oct 21
Event17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of
Duration: 2020 Oct 212020 Oct 24

Publication series

NameProceedings - International SoC Design Conference, ISOCC 2020


Conference17th International System-on-Chip Design Conference, ISOCC 2020
Country/TerritoryKorea, Republic of

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This work was supported by the MOTIE and KEIT [20012010, Design for Test of Intelligent Processors]

Publisher Copyright:
© 2020 IEEE.

All Science Journal Classification (ASJC) codes

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering
  • Instrumentation
  • Artificial Intelligence
  • Hardware and Architecture


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