Differential Read/Write 7T SRAM with Bit-Interleaved Structure for Near-Threshold Operation

Ji Sang Oh, Juhyun Park, Keonhee Cho, Tae Woo Oh, Seong Ook Jung

Research output: Contribution to journalArticlepeer-review

Abstract

Near-threshold voltage ( $V_{th}$ ) operation is an effective method for lowering energy consumption. However, it increases the impact of $V_{th}$ variation significantly, which makes it difficult for previously proposed static random access memory (SRAM) bitcells to achieve high read stability and write ability yields. To achieve these in the near- $V_{th}$ region, a differential 7T SRAM bitcell is proposed in which an additional row-based control signal and an nMOS transistor between the pull-up and pull-down transistors is adopted on one side of the cross-coupled inverter. In addition, the proposed SRAM bitcell can use a bit-interleaved structure without the half-select issue. Compared to differential 10T and 12T SRAM, the proposed differential 7T SRAM achieves 5% and 6% higher SRAM operating frequency and 70% and 23% lower operation energy consumption with a 33% and 49% smaller bitcell area, respectively.

Original languageEnglish
Article number9415630
Pages (from-to)64105-64115
Number of pages11
JournalIEEE Access
Volume9
DOIs
Publication statusPublished - 2021

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) under Grant 2021R1A2C2008297.

Publisher Copyright:
© 2013 IEEE.

All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Materials Science(all)
  • Engineering(all)

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