Direct current (DC) bias stress characteristics of a bottom-gate thin-film transistor with an amorphous/microcrystalline si double layer

Tae Hoon Jeong, Si Joon Kim, Hyun Jae Kim

Research output: Contribution to journalArticle

Abstract

In this paper, the bottom-gate thin-film transistors (TFTs) were fabricated with an amorphous/microcrystalline Si double layer (DL) as an active layer and the variations of the electrical characteristics were investigated according to the DC bias stresses. Since the fabrication process of DL TFTs was identical to that of the conventional amorphous Si (a-Si) TFTs, it creates no additional manufacturing cost. Moreover, the amorphous/microcrystalline Si DL could possibly improve stability and mass production efficiency. Although the field effect mobility of the typical DL TFTs is similar to that of a-Si TFTs, the DL TFTs had a higher reliability with respect to the direct current (DC) bias stresses.

Original languageEnglish
Pages (from-to)197-199
Number of pages3
JournalTransactions on Electrical and Electronic Materials
Volume12
Issue number5
DOIs
Publication statusPublished - 2011 Oct

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All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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