DRAM architecture for efficient data lifetime management

Yongjun Lee; Yunkeuk Kim; Jinkyu Jeong; Jae W. Lee

doi:10.1587/elex.14.20170309

DRAM architecture for efficient data lifetime management

Yongjun Lee, Yunkeuk Kim, Jinkyu Jeong, Jae W. Lee

Research output: Contribution to journal › Article › peer-review

Abstract

Many applications compute on sensitive data, such as confidential user information. Even if these applications are terminated, sensitive data often persist in the main memory indefinitely until the deallocated pages are overwritten by OS. The conventional software-only solution of zeroing pages at deallocation generates a significant amount of bursty memory traffic to slow down other processes running concurrently. To address this, we propose Secure DRAM, a novel DRAM architecture that enables low-cost, secure deallocation of physical page frames. By preventing access to unallocated DRAM pages and not refreshing them, Secure DRAM effectively closes the window of vulnerability with minimal performance overhead.

Original language	English
Article number	20170309
Journal	ieice electronics express
Volume	14
Issue number	10
DOIs	https://doi.org/10.1587/elex.14.20170309
Publication status	Published - 2017 Apr 26

Bibliographical note

Funding Information:
This research was supported by the National Research Foundation of Korea (NRF) grants funded by the Ministry of Science, ICT & Future Planning (MSIP) (NRF- 2014R1A1A1005894 and NRF-2017R1C1B2007273). Jae W. Lee is the corresponding author.

Publisher Copyright:
© IEICE 2017.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

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10.1587/elex.14.20170309

Cite this

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abstract = "Many applications compute on sensitive data, such as confidential user information. Even if these applications are terminated, sensitive data often persist in the main memory indefinitely until the deallocated pages are overwritten by OS. The conventional software-only solution of zeroing pages at deallocation generates a significant amount of bursty memory traffic to slow down other processes running concurrently. To address this, we propose Secure DRAM, a novel DRAM architecture that enables low-cost, secure deallocation of physical page frames. By preventing access to unallocated DRAM pages and not refreshing them, Secure DRAM effectively closes the window of vulnerability with minimal performance overhead.",

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DRAM architecture for efficient data lifetime management

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

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