DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores

Hyunggoy Oh, Inhyuk Choi, Sungho Kang

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


In the post-silicon debug of multicore designs, the debug time has increased significantly because the number of cores undergoing debug has increased; however the resources available to debug the design are limited. This paper proposes a new DRAM-based error detection method to overcome this challenge. The proposed method requires only three debug sessions even if multiple cores are present. The first debug session is used to detect the error intervals of each core using golden signatures. The second session is used to detect the error clock cycles in each core using a golden data stream. Instead of storing all of the golden data, the golden data stream is generated by selecting error-free debug data for each interval which are guaranteed by the first session. Finally, the error data in all cores are only captured during the third session. The experimental results on various debug cases show significant reductions in total debug time and the amount of DRAM usage compared to previous methods.

Original languageEnglish
Article number7872459
Pages (from-to)1504-1517
Number of pages14
JournalIEEE Transactions on Computers
Issue number9
Publication statusPublished - 2017 Sept 1

Bibliographical note

Funding Information:
This work was supported by a National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIP) (No. 2015R1A2A1A13001751). Sungho Kang is the corresponding author.

Publisher Copyright:
© 1968-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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