DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores

Hyunggoy Oh, Inhyuk Choi, Sungho Kang

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

In the post-silicon debug of multicore designs, the debug time has increased significantly because the number of cores undergoing debug has increased; however the resources available to debug the design are limited. This paper proposes a new DRAM-based error detection method to overcome this challenge. The proposed method requires only three debug sessions even if multiple cores are present. The first debug session is used to detect the error intervals of each core using golden signatures. The second session is used to detect the error clock cycles in each core using a golden data stream. Instead of storing all of the golden data, the golden data stream is generated by selecting error-free debug data for each interval which are guaranteed by the first session. Finally, the error data in all cores are only captured during the third session. The experimental results on various debug cases show significant reductions in total debug time and the amount of DRAM usage compared to previous methods.

Original languageEnglish
Article number7872459
Pages (from-to)1504-1517
Number of pages14
JournalIEEE Transactions on Computers
Volume66
Issue number9
DOIs
Publication statusPublished - 2017 Sep 1

Fingerprint

Error Detection
Dynamic random access storage
Error detection
Silicon
Data Streams
Interval
Clocks
Signature
Cycle
Resources
Experimental Results
Design

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

Cite this

@article{644ad97fd52c4c4990edf048dee1f5c3,
title = "DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores",
abstract = "In the post-silicon debug of multicore designs, the debug time has increased significantly because the number of cores undergoing debug has increased; however the resources available to debug the design are limited. This paper proposes a new DRAM-based error detection method to overcome this challenge. The proposed method requires only three debug sessions even if multiple cores are present. The first debug session is used to detect the error intervals of each core using golden signatures. The second session is used to detect the error clock cycles in each core using a golden data stream. Instead of storing all of the golden data, the golden data stream is generated by selecting error-free debug data for each interval which are guaranteed by the first session. Finally, the error data in all cores are only captured during the third session. The experimental results on various debug cases show significant reductions in total debug time and the amount of DRAM usage compared to previous methods.",
author = "Hyunggoy Oh and Inhyuk Choi and Sungho Kang",
year = "2017",
month = "9",
day = "1",
doi = "10.1109/TC.2017.2678504",
language = "English",
volume = "66",
pages = "1504--1517",
journal = "IEEE Transactions on Computers",
issn = "0018-9340",
publisher = "IEEE Computer Society",
number = "9",

}

DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores. / Oh, Hyunggoy; Choi, Inhyuk; Kang, Sungho.

In: IEEE Transactions on Computers, Vol. 66, No. 9, 7872459, 01.09.2017, p. 1504-1517.

Research output: Contribution to journalArticle

TY - JOUR

T1 - DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores

AU - Oh, Hyunggoy

AU - Choi, Inhyuk

AU - Kang, Sungho

PY - 2017/9/1

Y1 - 2017/9/1

N2 - In the post-silicon debug of multicore designs, the debug time has increased significantly because the number of cores undergoing debug has increased; however the resources available to debug the design are limited. This paper proposes a new DRAM-based error detection method to overcome this challenge. The proposed method requires only three debug sessions even if multiple cores are present. The first debug session is used to detect the error intervals of each core using golden signatures. The second session is used to detect the error clock cycles in each core using a golden data stream. Instead of storing all of the golden data, the golden data stream is generated by selecting error-free debug data for each interval which are guaranteed by the first session. Finally, the error data in all cores are only captured during the third session. The experimental results on various debug cases show significant reductions in total debug time and the amount of DRAM usage compared to previous methods.

AB - In the post-silicon debug of multicore designs, the debug time has increased significantly because the number of cores undergoing debug has increased; however the resources available to debug the design are limited. This paper proposes a new DRAM-based error detection method to overcome this challenge. The proposed method requires only three debug sessions even if multiple cores are present. The first debug session is used to detect the error intervals of each core using golden signatures. The second session is used to detect the error clock cycles in each core using a golden data stream. Instead of storing all of the golden data, the golden data stream is generated by selecting error-free debug data for each interval which are guaranteed by the first session. Finally, the error data in all cores are only captured during the third session. The experimental results on various debug cases show significant reductions in total debug time and the amount of DRAM usage compared to previous methods.

UR - http://www.scopus.com/inward/record.url?scp=85029504492&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85029504492&partnerID=8YFLogxK

U2 - 10.1109/TC.2017.2678504

DO - 10.1109/TC.2017.2678504

M3 - Article

AN - SCOPUS:85029504492

VL - 66

SP - 1504

EP - 1517

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 9

M1 - 7872459

ER -