Dual cache architecture for low cost and high performance

Jung Hoon Lee, Gi Ho Park, Shin Dug Kim

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. We show that the prefetch operation is highly accurate: over 90% of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance.

Original languageEnglish
Pages (from-to)275-287
Number of pages13
JournalETRI Journal
Issue number5
Publication statusPublished - 2003 Oct

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Computer Science(all)
  • Electrical and Electronic Engineering


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