Abstract
We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. We show that the prefetch operation is highly accurate: over 90% of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance.
| Original language | English |
|---|---|
| Pages (from-to) | 275-287 |
| Number of pages | 13 |
| Journal | ETRI Journal |
| Volume | 25 |
| Issue number | 5 |
| DOIs | |
| Publication status | Published - 2003 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Computer Science(all)
- Electrical and Electronic Engineering
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Dual cache architecture for low cost and high performance. / Lee, Jung Hoon; Park, Gi Ho; Kim, Shin-Dug.
In: ETRI Journal, Vol. 25, No. 5, 01.01.2003, p. 275-287.Research output: Contribution to journal › Article
TY - JOUR
T1 - Dual cache architecture for low cost and high performance
AU - Lee, Jung Hoon
AU - Park, Gi Ho
AU - Kim, Shin-Dug
PY - 2003/1/1
Y1 - 2003/1/1
N2 - We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. We show that the prefetch operation is highly accurate: over 90% of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance.
AB - We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. We show that the prefetch operation is highly accurate: over 90% of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance.
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UR - http://www.scopus.com/inward/citedby.url?scp=0242323541&partnerID=8YFLogxK
U2 - 10.4218/etrij.03.0303.0015
DO - 10.4218/etrij.03.0303.0015
M3 - Article
AN - SCOPUS:0242323541
VL - 25
SP - 275
EP - 287
JO - ETRI Journal
JF - ETRI Journal
SN - 1225-6463
IS - 5
ER -