Dual cache architecture for low cost and high performance

Jung Hoon Lee, Gi Ho Park, Shin-Dug Kim

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. We show that the prefetch operation is highly accurate: over 90% of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance.

Original languageEnglish
Pages (from-to)275-287
Number of pages13
JournalETRI Journal
Volume25
Issue number5
DOIs
Publication statusPublished - 2003 Jan 1

Fingerprint

Buffers
Hardware
Monitoring
Costs

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Computer Science(all)
  • Electrical and Electronic Engineering

Cite this

Lee, Jung Hoon ; Park, Gi Ho ; Kim, Shin-Dug. / Dual cache architecture for low cost and high performance. In: ETRI Journal. 2003 ; Vol. 25, No. 5. pp. 275-287.
@article{ed9b3491c9764f0bacef85191a17dfb8,
title = "Dual cache architecture for low cost and high performance",
abstract = "We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. We show that the prefetch operation is highly accurate: over 90{\%} of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance.",
author = "Lee, {Jung Hoon} and Park, {Gi Ho} and Shin-Dug Kim",
year = "2003",
month = "1",
day = "1",
doi = "10.4218/etrij.03.0303.0015",
language = "English",
volume = "25",
pages = "275--287",
journal = "ETRI Journal",
issn = "1225-6463",
publisher = "ETRI",
number = "5",

}

Dual cache architecture for low cost and high performance. / Lee, Jung Hoon; Park, Gi Ho; Kim, Shin-Dug.

In: ETRI Journal, Vol. 25, No. 5, 01.01.2003, p. 275-287.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Dual cache architecture for low cost and high performance

AU - Lee, Jung Hoon

AU - Park, Gi Ho

AU - Kim, Shin-Dug

PY - 2003/1/1

Y1 - 2003/1/1

N2 - We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. We show that the prefetch operation is highly accurate: over 90% of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance.

AB - We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. We show that the prefetch operation is highly accurate: over 90% of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance.

UR - http://www.scopus.com/inward/record.url?scp=0242323541&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0242323541&partnerID=8YFLogxK

U2 - 10.4218/etrij.03.0303.0015

DO - 10.4218/etrij.03.0303.0015

M3 - Article

AN - SCOPUS:0242323541

VL - 25

SP - 275

EP - 287

JO - ETRI Journal

JF - ETRI Journal

SN - 1225-6463

IS - 5

ER -