We introduce a new dual threshold voltage technique for domino logic. Since domino logic is much more sensitive to noise, noise margins have to be taken into account when applying dual threshold voltages to domino logic. To guarantee the signal integrity in domino logic, we carefully consider the effect of transistor sizing and threshold voltage selection. For optimal design, tradeoffs need to be mad? among noise margin, power, and performance. Based on the characteristics of each logic gate, we propose noise and power constrained domino logic synthesis for high performance. ISCAS85 benchmark re sults show that performance can be improved up to 18.62%, with 2% active power increase, while maintaining noise margin.
|Number of pages||6|
|Journal||Proceedings -Design, Automation and Test in Europe, DATE|
|Publication status||Published - 2002 Dec 1|
|Event||2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 - Paris, France|
Duration: 2002 Mar 4 → 2002 Mar 8
All Science Journal Classification (ASJC) codes