Dual threshold voltage domino logic synthesis for high performance with noise and power constraint

Seong Ook Jung, Ki Wook Kim, Sung Mo Kang

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

We introduce a new dual threshold voltage technique for domino logic. Since domino logic is much more sensitive to noise, noise margins have to be taken into account when applying dual threshold voltages to domino logic. To guarantee the signal integrity in domino logic, we carefully consider the effect of transistor sizing and threshold voltage selection. For optimal design, tradeoffs need to be mad? among noise margin, power, and performance. Based on the characteristics of each logic gate, we propose noise and power constrained domino logic synthesis for high performance. ISCAS85 benchmark re sults show that performance can be improved up to 18.62%, with 2% active power increase, while maintaining noise margin.

Original languageEnglish
Article number998282
Pages (from-to)260-265
Number of pages6
JournalProceedings -Design, Automation and Test in Europe, DATE
DOIs
Publication statusPublished - 2002 Dec 1
Event2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 - Paris, France
Duration: 2002 Mar 42002 Mar 8

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Fingerprint Dive into the research topics of 'Dual threshold voltage domino logic synthesis for high performance with noise and power constraint'. Together they form a unique fingerprint.

  • Cite this