Main memory systems have gone through dramatic increases in bandwidth and capacity. At the same time, their random access latency has remained relatively constant. For given memory technology, optimizing the latency typically requires sacrificing the density (i.e., cost per bit), which is one of the most critical concerns for memory industry. Recent studies have proposed memory architectures comprised of asymmetric (fast/low-density and slow/high-density) regions to optimize between overall latency and negative impact on density. Such memory architectures attempt to cost-effectively offer both high capacity and high performance. Yet they present a unique challenge, requiring direct placements of hot memory pages1 in the fast region and/or expensive runtime page migrations. In this paper, we propose a novel resistive memory architecture sharing a set of row buffers between a pair of neighboring banks. It enables two attractive techniques: (1) migrating memory pages between slow and fast banks with little performance overhead and (2) adaptively allocating more row buffers to busier banks based on memory access patterns. For an asymmetric memory architecture with both slow/high-density and fast/low-density banks, our shared row-buffer architecture can capture 87-93% of the performance of a memory architecture with only fast banks.
|Title of host publication||Proceedings of the 2016 IEEE International Symposium on High-Performance Computer Architecture, HPCA 2016|
|Publisher||IEEE Computer Society|
|Number of pages||13|
|Publication status||Published - 2016 Apr 1|
|Event||22nd IEEE International Symposium on High Performance Computer Architecture, HPCA 2016 - Barcelona, Spain|
Duration: 2016 Mar 12 → 2016 Mar 16
|Name||Proceedings - International Symposium on High-Performance Computer Architecture|
|Other||22nd IEEE International Symposium on High Performance Computer Architecture, HPCA 2016|
|Period||16/3/12 → 16/3/16|
Bibliographical noteFunding Information:
This research was supported in part by NSF (CNS-1217102 and CNS-1557244) and MSIP (Ministry of Science, ICT and Future Planning), Korea, under the IT Consilience Creative Program (IITP-2015-R0346-15-1008) supervised by NIPA (National IT Industry Promotion Agency). Nam Sung Kim has a financial interest in AMD and Samsung Semiconductor.
© 2016 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture