Abstract
We present a selective filter-bank translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks, with a small two-bank buffer, called as a filter-bank buffer, located above its associated bank. Either a filter-bank buffer or a main bank TLB can be selectively accessed based on two bits in the filter-bank buffer. Power savings are achieved by reducing the number of entries accessed at a time, by using filtering and bank mechanism. The overhead of the proposed TLB turns out to be negligible compared with other hierarchical structures. That is, the two-cycle overhead of the proposed TLB is only about 3%, as compared with the 6% overhead of filter (micro)-TLB and the 9% overhead of banked-filter TLB. We show that the average hit ratios of the filter-bank buffers and the main banks of the proposed TLB are 88 and 12%, respectively. Therefore, significant power savings can be achieved with just a small performance degradation. The Power × Delay product can be reduced by about 88% compared with a fully associative TLB, 67% with respect to filter-TLB, and 37% relative to banked-filter TLB.
| Original language | English |
|---|---|
| Pages (from-to) | 95-105 |
| Number of pages | 11 |
| Journal | Microprocessors and Microsystems |
| Volume | 28 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 2004 Apr 23 |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Computer Networks and Communications
- Artificial Intelligence
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Dynamic and selective low power data TLB system. / Lee, Jung Hoon; Park, Gi Ho; Kim, Shin-Dug.
In: Microprocessors and Microsystems, Vol. 28, No. 3, 23.04.2004, p. 95-105.Research output: Contribution to journal › Article
TY - JOUR
T1 - Dynamic and selective low power data TLB system
AU - Lee, Jung Hoon
AU - Park, Gi Ho
AU - Kim, Shin-Dug
PY - 2004/4/23
Y1 - 2004/4/23
N2 - We present a selective filter-bank translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks, with a small two-bank buffer, called as a filter-bank buffer, located above its associated bank. Either a filter-bank buffer or a main bank TLB can be selectively accessed based on two bits in the filter-bank buffer. Power savings are achieved by reducing the number of entries accessed at a time, by using filtering and bank mechanism. The overhead of the proposed TLB turns out to be negligible compared with other hierarchical structures. That is, the two-cycle overhead of the proposed TLB is only about 3%, as compared with the 6% overhead of filter (micro)-TLB and the 9% overhead of banked-filter TLB. We show that the average hit ratios of the filter-bank buffers and the main banks of the proposed TLB are 88 and 12%, respectively. Therefore, significant power savings can be achieved with just a small performance degradation. The Power × Delay product can be reduced by about 88% compared with a fully associative TLB, 67% with respect to filter-TLB, and 37% relative to banked-filter TLB.
AB - We present a selective filter-bank translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks, with a small two-bank buffer, called as a filter-bank buffer, located above its associated bank. Either a filter-bank buffer or a main bank TLB can be selectively accessed based on two bits in the filter-bank buffer. Power savings are achieved by reducing the number of entries accessed at a time, by using filtering and bank mechanism. The overhead of the proposed TLB turns out to be negligible compared with other hierarchical structures. That is, the two-cycle overhead of the proposed TLB is only about 3%, as compared with the 6% overhead of filter (micro)-TLB and the 9% overhead of banked-filter TLB. We show that the average hit ratios of the filter-bank buffers and the main banks of the proposed TLB are 88 and 12%, respectively. Therefore, significant power savings can be achieved with just a small performance degradation. The Power × Delay product can be reduced by about 88% compared with a fully associative TLB, 67% with respect to filter-TLB, and 37% relative to banked-filter TLB.
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U2 - 10.1016/j.micpro.2003.12.001
DO - 10.1016/j.micpro.2003.12.001
M3 - Article
VL - 28
SP - 95
EP - 105
JO - Microprocessors and Microsystems
JF - Microprocessors and Microsystems
SN - 0141-9331
IS - 3
ER -