Dynamic and selective low power data TLB system

We present a selective filter-bank translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks, with a small two-bank buffer, called as a filter-bank buffer, located above its associated bank. Either a filter-bank buffer or a main bank TLB can be selectively accessed based on two bits in the filter-bank buffer. Power savings are achieved by reducing the number of entries accessed at a time, by using filtering and bank mechanism. The overhead of the proposed TLB turns out to be negligible compared with other hierarchical structures. That is, the two-cycle overhead of the proposed TLB is only about 3%, as compared with the 6% overhead of filter (micro)-TLB and the 9% overhead of banked-filter TLB. We show that the average hit ratios of the filter-bank buffers and the main banks of the proposed TLB are 88 and 12%, respectively. Therefore, significant power savings can be achieved with just a small performance degradation. The Power × Delay product can be reduced by about 88% compared with a fully associative TLB, 67% with respect to filter-TLB, and 37% relative to banked-filter TLB.