As advances in memory density and capacity result in an increase in the probability of fault occurrence, many studies on built-in redundancy analysis (BIRA) have been conducted to address this problem. However, conventional BIRAs cannot directly find a final repair solution as soon as test sequences of the built-in self-test (BIST) are over, because they require starting the fault analyses after finishing the test sequences to achieve an optimal repair rate. For this reason, additional analysis time is inevitable, which affects total test costs. In this paper, a dynamic BIRA is proposed for memory repair. It can find a final repair solution directly as soon as test sequences if the BIST are over and achieve an optimal repair rate. The proposed BIRA can restore faults in fault-storing content-addressable memories whenever the spaces in them can be reduced via dynamic fault analysis. Furthermore, the proposed BIRA can be implemented with a reasonable hardware size. This is demonstrated via experiments.
|Number of pages||10|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Publication status||Published - 2019 Oct|
Bibliographical noteFunding Information:
Manuscript received December 11, 2018; revised March 24, 2019 and May 10, 2019; accepted June 1, 2019. Date of publication June 26, 2019; date of current version September 25, 2019.This research was supported by the MOTIE (Ministry of Trade, Industry and Energy (10052875) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. (Corresponding author: Sungho Kang.) The authors are with the Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: firstname.lastname@example.org; email@example.com; firstname.lastname@example.org; email@example.com).
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering