Abstract
A novel dynamic mixed serial-parallel content addressable memory (DMSP CAM) is proposed to achieve both low-power consumption and high performance. The replica circuits provide optimal timings to enable and disable the matchline charge transistor, which maximizes performance and minimizes leakage current, respectively. The DMSP CAM does not suffer from charge sharing in the serial stage and achieves high performance by removing the predischarge or precharge operation of the matchline before every comparison. To guarantee the robustness of the proposed scheme, a statistical design methodology is also applied. Using the 45-nm technology, the DMSP CAM achieves both energy saving and performance improvement, and thus over 53% energy-delay product reduction compared with the other serial-parallel mixed CAMs.
| Original language | English |
|---|---|
| Pages (from-to) | 721-731 |
| Number of pages | 11 |
| Journal | International Journal of Circuit Theory and Applications |
| Volume | 41 |
| Issue number | 7 |
| DOIs | |
| Publication status | Published - 2013 Jul 1 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Computer Science Applications
- Electrical and Electronic Engineering
- Applied Mathematics
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Dynamic mixed serial-parallel content addressable memory (DMSP CAM). / Kang, Mingu; Kim, Jisu; Yang, Young Hwi; Jung, Seong Ook.
In: International Journal of Circuit Theory and Applications, Vol. 41, No. 7, 01.07.2013, p. 721-731.Research output: Contribution to journal › Article
TY - JOUR
T1 - Dynamic mixed serial-parallel content addressable memory (DMSP CAM)
AU - Kang, Mingu
AU - Kim, Jisu
AU - Yang, Young Hwi
AU - Jung, Seong Ook
PY - 2013/7/1
Y1 - 2013/7/1
N2 - A novel dynamic mixed serial-parallel content addressable memory (DMSP CAM) is proposed to achieve both low-power consumption and high performance. The replica circuits provide optimal timings to enable and disable the matchline charge transistor, which maximizes performance and minimizes leakage current, respectively. The DMSP CAM does not suffer from charge sharing in the serial stage and achieves high performance by removing the predischarge or precharge operation of the matchline before every comparison. To guarantee the robustness of the proposed scheme, a statistical design methodology is also applied. Using the 45-nm technology, the DMSP CAM achieves both energy saving and performance improvement, and thus over 53% energy-delay product reduction compared with the other serial-parallel mixed CAMs.
AB - A novel dynamic mixed serial-parallel content addressable memory (DMSP CAM) is proposed to achieve both low-power consumption and high performance. The replica circuits provide optimal timings to enable and disable the matchline charge transistor, which maximizes performance and minimizes leakage current, respectively. The DMSP CAM does not suffer from charge sharing in the serial stage and achieves high performance by removing the predischarge or precharge operation of the matchline before every comparison. To guarantee the robustness of the proposed scheme, a statistical design methodology is also applied. Using the 45-nm technology, the DMSP CAM achieves both energy saving and performance improvement, and thus over 53% energy-delay product reduction compared with the other serial-parallel mixed CAMs.
UR - http://www.scopus.com/inward/record.url?scp=84880321837&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84880321837&partnerID=8YFLogxK
U2 - 10.1002/cta.814
DO - 10.1002/cta.814
M3 - Article
AN - SCOPUS:84880321837
VL - 41
SP - 721
EP - 731
JO - International Journal of Circuit Theory and Applications
JF - International Journal of Circuit Theory and Applications
SN - 0098-9886
IS - 7
ER -