Dynamic power supply current test for CMOS SRAM

Doe Hyun Yoon, Hong Sik Kim, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

This paper presents the relationship between the dynamic power supply current and the switching behavior of an SRAM cell. Compared to a fault free cell, how the short, open and coupling faults can affect the peak value of a dynamic current pulse when a transition write is performed, is analyzed. In addition, the test for linked idempotent coupling faults is proposed. This new approach has reduced test length compared to the previous March B test. Finally the low overhead built-in current sensor that can detect a dynamic current pulse and distinguish its peak value, is proposed.

Original languageEnglish
Title of host publicationICVC 1999 - 6th International Conference on VLSI and CAD
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages399-402
Number of pages4
ISBN (Print)0780357272, 9780780357273
DOIs
Publication statusPublished - 1999 Jan 1
Event6th International Conference on VLSI and CAD, ICVC 1999 - Seoul, Korea, Republic of
Duration: 1999 Oct 261999 Oct 27

Other

Other6th International Conference on VLSI and CAD, ICVC 1999
CountryKorea, Republic of
CitySeoul
Period99/10/2699/10/27

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All Science Journal Classification (ASJC) codes

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Yoon, D. H., Kim, H. S., & Kang, S. (1999). Dynamic power supply current test for CMOS SRAM. In ICVC 1999 - 6th International Conference on VLSI and CAD (pp. 399-402). [820944] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICVC.1999.820944