In order to gain market share in today's competitive high-tech industry, fast time-to-market (TTM) is one of the key factors for the success of a product. Since pre-silicon verification cannot be applied exhaustively as the size and complexity of the integrated circuit design increases, post-silicon validation becomes crucial to capture bugs and design errors that escape from the pre-silicon verification phase. However, because of the limited observability of internal states due to the limited storage capacity available for post-silicon validation, selecting optimal sets of trace signals has always been a challenging task for debugging engineers. This paper proposes a new dynamic trace signal selection algorithm to maximize the restoration ratio for internal circuit states. Experimental results on benchmark circuits and an industry design show that the proposed technique provides a high degree of state restoration regardless of the input test patterns.