The NTV circuit has been introduced as a new low power design concept, which increases energy efficiency significantly. However, delay sensitivity of the NTV circuit is a major challenge. In addition, this problem can be more critical during at-speed scan test because of the dynamic voltage drop issue. In this paper, we propose a comparison of dynamic voltage drop induced path delay between STV and NTV circuits during at-speed scan test. To the best knowledge of the authors, it is the first time to analyze the voltage drop induced path delay during the NTV circuit scan test. Experimental results show that the path delay increment of NTV is larger than that of STV although the dynamic voltage drop of NTV is smaller than that of STV.
|Title of host publication||Proceedings - International SoC Design Conference 2018, ISOCC 2018|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2019 Feb 22|
|Event||15th International SoC Design Conference, ISOCC 2018 - Daegu, Korea, Republic of|
Duration: 2018 Nov 12 → 2018 Nov 15
|Name||Proceedings - International SoC Design Conference 2018, ISOCC 2018|
|Conference||15th International SoC Design Conference, ISOCC 2018|
|Country||Korea, Republic of|
|Period||18/11/12 → 18/11/15|
Bibliographical noteFunding Information:
This work was supported by the IT R&D program of MOTIE/KEIT. [10052716, Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC].
ACKNOWLEDGMENT This research was partially supported by the Graduate School of YONSEI University Research Scholarship Grants in 2018.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials