Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test

Hyunggoy Oh, Heetae Kim, Sangjun Lee, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The NTV circuit has been introduced as a new low power design concept, which increases energy efficiency significantly. However, delay sensitivity of the NTV circuit is a major challenge. In addition, this problem can be more critical during at-speed scan test because of the dynamic voltage drop issue. In this paper, we propose a comparison of dynamic voltage drop induced path delay between STV and NTV circuits during at-speed scan test. To the best knowledge of the authors, it is the first time to analyze the voltage drop induced path delay during the NTV circuit scan test. Experimental results show that the path delay increment of NTV is larger than that of STV although the dynamic voltage drop of NTV is smaller than that of STV.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2018, ISOCC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages7-8
Number of pages2
ISBN (Electronic)9781538679609
DOIs
Publication statusPublished - 2019 Feb 22
Event15th International SoC Design Conference, ISOCC 2018 - Daegu, Korea, Republic of
Duration: 2018 Nov 122018 Nov 15

Publication series

NameProceedings - International SoC Design Conference 2018, ISOCC 2018

Conference

Conference15th International SoC Design Conference, ISOCC 2018
CountryKorea, Republic of
CityDaegu
Period18/11/1218/11/15

Fingerprint

Networks (circuits)
Energy efficiency
Voltage drop

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Oh, H., Kim, H., Lee, S., & Kang, S. (2019). Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test. In Proceedings - International SoC Design Conference 2018, ISOCC 2018 (pp. 7-8). [8649911] (Proceedings - International SoC Design Conference 2018, ISOCC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2018.8649911
Oh, Hyunggoy ; Kim, Heetae ; Lee, Sangjun ; Kang, Sungho. / Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test. Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 7-8 (Proceedings - International SoC Design Conference 2018, ISOCC 2018).
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abstract = "The NTV circuit has been introduced as a new low power design concept, which increases energy efficiency significantly. However, delay sensitivity of the NTV circuit is a major challenge. In addition, this problem can be more critical during at-speed scan test because of the dynamic voltage drop issue. In this paper, we propose a comparison of dynamic voltage drop induced path delay between STV and NTV circuits during at-speed scan test. To the best knowledge of the authors, it is the first time to analyze the voltage drop induced path delay during the NTV circuit scan test. Experimental results show that the path delay increment of NTV is larger than that of STV although the dynamic voltage drop of NTV is smaller than that of STV.",
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Oh, H, Kim, H, Lee, S & Kang, S 2019, Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test. in Proceedings - International SoC Design Conference 2018, ISOCC 2018., 8649911, Proceedings - International SoC Design Conference 2018, ISOCC 2018, Institute of Electrical and Electronics Engineers Inc., pp. 7-8, 15th International SoC Design Conference, ISOCC 2018, Daegu, Korea, Republic of, 18/11/12. https://doi.org/10.1109/ISOCC.2018.8649911

Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test. / Oh, Hyunggoy; Kim, Heetae; Lee, Sangjun; Kang, Sungho.

Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 7-8 8649911 (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Oh H, Kim H, Lee S, Kang S. Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test. In Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 7-8. 8649911. (Proceedings - International SoC Design Conference 2018, ISOCC 2018). https://doi.org/10.1109/ISOCC.2018.8649911