Effect of Floating Gate Insertion on the Analog States of Ferroelectric Field-Effect Transistors

Sangho Lee, Youngkyu Lee, Giuk Kim, Taeho Kim, Taehyong Eom, Seong Ook Jung, Sanghun Jeon

Research output: Contribution to journalArticlepeer-review


In this work, we propose a structural approach to mitigate device-to-device variation and performance degradation of ferroelectric (FE) field-effect transistors (FeFETs) due to the inhomogeneity of FE and dielectric (DE) phases of the FE layer. We found that by inserting a floating gate below the FE layer, the polarization effect of FE grains is equalized, thus suppressing the formation of an undesired current percolation path through the channel of the FeFET. This also results in a wider memory window and improved device variation, which ultimately improves the accuracy of in-memory computing. We believe that the proposed approach could be an important strategy enabling reliable and unified operation of FeFETs with the scaling of device.

Original languageEnglish
Pages (from-to)349-353
Number of pages5
JournalIEEE Transactions on Electron Devices
Issue number1
Publication statusPublished - 2023 Jan 1

Bibliographical note

Funding Information:
This work was supported by the IC Design Education Center (IDEC) at EDA tool under Grant NRF-2020M3F3A2A02082436 and Grant NRF-2020M3F3A2A01081916

Publisher Copyright:
© 1963-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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