Effect of gate hard mask and sidewall spacer structures on the gate oxide reliability of W/WN_x/poly-Si gate MOSFET for high density DRAM applications

We have studied the effects of the gate hard mask and the gate spacer nitride film on the reliability of WW Nx poly-Si gated devices. When the gate hard mask nitride film is used, severe degradation of the stress-induced leakage current (SILC) and the interface trap density (Dit) characteristics are observed in the large metal-oxide-semiconductor (MOS) capacitors. On the other hand, as the devices become smaller, the effects of the hard mask nitride film are relieved. The gate spacer stack plays a more critical role in the reliability of smaller devices. The oxidenitride (ON) spacered devices exhibit better reliability in terms of SILC, Dit, threshold voltage (Vth) shift, and transconductance (Gm) compared to those of the nitrideoxidenitride (NON) spacered ones. These behaviors are explained by the mechanical stress of the nitride films.