Effect of gate hard mask and sidewall spacer structures on the gate oxide reliability of W/WNx/poly-Si gate MOSFET for high density DRAM applications

Kwan Yong Lim, Heung Jae Cho, Se Aug Jang, Yong Soo Kim, Jae Geun Oh, Jung Ho Lee, Hong Seon Yang, Hyun Chul Sohn, Jin Woong Kim

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

We have studied the effects of the gate hard mask and the gate spacer nitride film on the reliability of WW Nx poly-Si gated devices. When the gate hard mask nitride film is used, severe degradation of the stress-induced leakage current (SILC) and the interface trap density (Dit) characteristics are observed in the large metal-oxide-semiconductor (MOS) capacitors. On the other hand, as the devices become smaller, the effects of the hard mask nitride film are relieved. The gate spacer stack plays a more critical role in the reliability of smaller devices. The oxidenitride (ON) spacered devices exhibit better reliability in terms of SILC, Dit, threshold voltage (Vth) shift, and transconductance (Gm) compared to those of the nitrideoxidenitride (NON) spacered ones. These behaviors are explained by the mechanical stress of the nitride films.

Original languageEnglish
Pages (from-to)1036-1040
Number of pages5
JournalJournal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
Volume23
Issue number3
DOIs
Publication statusPublished - 2005 Dec 1

All Science Journal Classification (ASJC) codes

  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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