Silicon german ium (SiGe) has attracted significant attention for applications in the source/drain (S/D) regions of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs). However, in SiGe, as the Ge concentration increases, high-density defects are generated, which limit its applications. Therefore, several techniques have been developed to minimize defects; however, these techniques require relatively thick epitaxial layers and are not suitable for gate-all-around FETs. This study examined the effect of Ge concentration on the embedded SiGe source/drain region of a logic p-MOSFET. The strain was calculated through nano-beam diffraction and predictions through a simulation were compared to understand the effects of stress relaxation on the change in strain applied to the Si channel. When the device performance was evaluated, the drain saturation current was approximately 710 µA/µm at an off current of 100 nA/µm with a drain voltage of 1 V, indicating that the current was enhanced by 58% when the Ge concentration was optimized.
Bibliographical noteFunding Information:
This work was supported by the Technology Innovation Program (1415173045) funded by the Ministry of Trade, Industry & Energy (MOTIE) and Future Semiconductor Device Technology Development Program (10067739) funded by the MOTIE and Korea Semiconductor Research Consortium (KSRC).
© 2021 by the authors. Licensee MDPI, Basel, Switzerland.
All Science Journal Classification (ASJC) codes
- Surfaces and Interfaces
- Surfaces, Coatings and Films
- Materials Chemistry