Effect of selectively passivated layer on foldable low temperature polycrystalline silicon thin film transistor characteristics under dynamic mechanical stress

Sang Myung Lee, Ilgu Yun

Research output: Contribution to journalArticle

Abstract

For the next generation display, foldable display is one of the attractive candidates. However, the degradation effects due to the mechanical stress on the device are unavoidable. A strain due to the mechanical stress generates cracks on the thin film transistors (TFTs). In this case, if the methodology guiding cracks is applied in the fabrication process, the device reliability can be enhanced. In this paper, a crack guided layer followed by the device fabrication process is deposited on p-type low temperature polycrystalline silicon (LTPS) TFT. Statistical analysis is also used to analyze the crack guided layer effects. To apply a strain on the foldable LTPS TFTS, 5000 cycles of dynamic mechanical stress with tensile and perpendicular directions were applied with 2-mm bending radius. Based on the results, TFT reliability can be enhanced by controlled the crack position using the crack-guided passivation layer.

Original languageEnglish
Pages (from-to)606-609
Number of pages4
JournalMicroelectronics Reliability
Volume76-77
DOIs
Publication statusPublished - 2017 Sep 1

Fingerprint

Thin film transistors
Polysilicon
transistors
cracks
Cracks
silicon
thin films
Temperature
Display devices
Fabrication
fabrication
Passivation
statistical analysis
passivity
Statistical methods
methodology
degradation
Degradation
cycles
radii

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Safety, Risk, Reliability and Quality
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

Cite this

@article{01d6fbd00479434e9524ab594a1819b3,
title = "Effect of selectively passivated layer on foldable low temperature polycrystalline silicon thin film transistor characteristics under dynamic mechanical stress",
abstract = "For the next generation display, foldable display is one of the attractive candidates. However, the degradation effects due to the mechanical stress on the device are unavoidable. A strain due to the mechanical stress generates cracks on the thin film transistors (TFTs). In this case, if the methodology guiding cracks is applied in the fabrication process, the device reliability can be enhanced. In this paper, a crack guided layer followed by the device fabrication process is deposited on p-type low temperature polycrystalline silicon (LTPS) TFT. Statistical analysis is also used to analyze the crack guided layer effects. To apply a strain on the foldable LTPS TFTS, 5000 cycles of dynamic mechanical stress with tensile and perpendicular directions were applied with 2-mm bending radius. Based on the results, TFT reliability can be enhanced by controlled the crack position using the crack-guided passivation layer.",
author = "Lee, {Sang Myung} and Ilgu Yun",
year = "2017",
month = "9",
day = "1",
doi = "10.1016/j.microrel.2017.07.092",
language = "English",
volume = "76-77",
pages = "606--609",
journal = "Microelectronics Reliability",
issn = "0026-2714",
publisher = "Elsevier Limited",

}

TY - JOUR

T1 - Effect of selectively passivated layer on foldable low temperature polycrystalline silicon thin film transistor characteristics under dynamic mechanical stress

AU - Lee, Sang Myung

AU - Yun, Ilgu

PY - 2017/9/1

Y1 - 2017/9/1

N2 - For the next generation display, foldable display is one of the attractive candidates. However, the degradation effects due to the mechanical stress on the device are unavoidable. A strain due to the mechanical stress generates cracks on the thin film transistors (TFTs). In this case, if the methodology guiding cracks is applied in the fabrication process, the device reliability can be enhanced. In this paper, a crack guided layer followed by the device fabrication process is deposited on p-type low temperature polycrystalline silicon (LTPS) TFT. Statistical analysis is also used to analyze the crack guided layer effects. To apply a strain on the foldable LTPS TFTS, 5000 cycles of dynamic mechanical stress with tensile and perpendicular directions were applied with 2-mm bending radius. Based on the results, TFT reliability can be enhanced by controlled the crack position using the crack-guided passivation layer.

AB - For the next generation display, foldable display is one of the attractive candidates. However, the degradation effects due to the mechanical stress on the device are unavoidable. A strain due to the mechanical stress generates cracks on the thin film transistors (TFTs). In this case, if the methodology guiding cracks is applied in the fabrication process, the device reliability can be enhanced. In this paper, a crack guided layer followed by the device fabrication process is deposited on p-type low temperature polycrystalline silicon (LTPS) TFT. Statistical analysis is also used to analyze the crack guided layer effects. To apply a strain on the foldable LTPS TFTS, 5000 cycles of dynamic mechanical stress with tensile and perpendicular directions were applied with 2-mm bending radius. Based on the results, TFT reliability can be enhanced by controlled the crack position using the crack-guided passivation layer.

UR - http://www.scopus.com/inward/record.url?scp=85028081991&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85028081991&partnerID=8YFLogxK

U2 - 10.1016/j.microrel.2017.07.092

DO - 10.1016/j.microrel.2017.07.092

M3 - Article

VL - 76-77

SP - 606

EP - 609

JO - Microelectronics Reliability

JF - Microelectronics Reliability

SN - 0026-2714

ER -