Effect of Si interlayer thickness and post-metallization annealing on Ge MOS capacitor on Ge-on-Si substrate

Ook Sang Yoo, Jungwoo Oh, Chang Yong Kang, Byoung Hun Lee, In Shik Han, Won Ho Choi, Hyuk Min Kwon, Min Ki Na, Prashant Majhi, Hsing Huang Tseng, Raj Jammy, Jin Suk Wang, Hi Deok Lee

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Abstract

We demonstrated the effect of post-metallization annealing and Si interlayer thickness on Ge MOS capacitor on Ge-on-Si substrate with HfO2/TaN. Ge outdiffusion and oxygen interdiffusion were completely suppressed by thick Si interfacial layer. As a result, formation of insufficient low-k Ge oxides was effectively inhibited. It is confirmed that gate current of Si passivated Ge MOS was decreased by Si IL and decrease of gate current, Jg is saturated after Si IL of 2 nm. It was also observed that when Si IL is thick enough to restrict Ge outdiffusion, increase of Jg is not due to the temperature-induced Ge outdiffusion but due to the partial crystallization of HfO2 at higher annealing temperature.

Original languageEnglish
Pages (from-to)102-105
Number of pages4
JournalMaterials Science and Engineering B: Solid-State Materials for Advanced Technology
Volume154-155
Issue number1-3
DOIs
Publication statusPublished - 2008 Dec 5

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All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

Cite this

Yoo, O. S., Oh, J., Kang, C. Y., Lee, B. H., Han, I. S., Choi, W. H., Kwon, H. M., Na, M. K., Majhi, P., Tseng, H. H., Jammy, R., Wang, J. S., & Lee, H. D. (2008). Effect of Si interlayer thickness and post-metallization annealing on Ge MOS capacitor on Ge-on-Si substrate. Materials Science and Engineering B: Solid-State Materials for Advanced Technology, 154-155(1-3), 102-105. https://doi.org/10.1016/j.mseb.2008.06.031