Effect of SiO2 tunnel layer processes on the characteristics of MONOS charge trap devices with poly-Si channels

Heedo Na, Jinho Oh, Kyumin Lee, Jonggi Kim, Sunghoon Lee, Dong Hyeok Lim, Mann Ho Cho, Hyunchul Sohn

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

In this study, we investigated the effect of various SiO2 tunnel layers on the characteristics of charge trap memories with Metal/SiO 2/Si3N4/SiO2/n-type poly-Si (MONOS) structures. For MONOS devices, SiO2 tunnel layers were formed on poly-Si channels using thermal oxidation, radical oxidation, and LP-CVD. We investigated the characteristics of each SiO2 tunnel layer on poly-Si including breakdown, leakage current and FN tunneling. Radical SiO2 and LP-TEOS SiO2 showed larger breakdown voltages with more uniform thickness than thermal SiO2 on poly-Si channels. MONOS devices with radical SiO2 and LP-TEOS SiO2 tunnel layers showed improved program/erase (P/E) and endurance compared with thermal SiO 2. In particular, the MONOS device with LP-TEOS SiO2 showed the largest memory window with the fastest P/E operation, which was attributed to enhanced defect-assisted tunneling in LP-TEOS SiO2. The endurances of MONOS devices were measured and related to the flat-band voltage shift in conjunction with trapped charge types in SiO2 tunnel dielectrics.

Original languageEnglish
Pages (from-to)6-11
Number of pages6
JournalMicroelectronic Engineering
Volume110
DOIs
Publication statusPublished - 2013 May 27

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Polysilicon
tunnels
Tunnels
traps
endurance
Durability
Data storage equipment
Oxidation
oxidation
Electric breakdown
electrical faults
Leakage currents
Chemical vapor deposition
leakage
breakdown
Metals
vapor deposition
Defects
shift
defects

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

Cite this

Na, Heedo ; Oh, Jinho ; Lee, Kyumin ; Kim, Jonggi ; Lee, Sunghoon ; Lim, Dong Hyeok ; Cho, Mann Ho ; Sohn, Hyunchul. / Effect of SiO2 tunnel layer processes on the characteristics of MONOS charge trap devices with poly-Si channels. In: Microelectronic Engineering. 2013 ; Vol. 110. pp. 6-11.
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Effect of SiO2 tunnel layer processes on the characteristics of MONOS charge trap devices with poly-Si channels. / Na, Heedo; Oh, Jinho; Lee, Kyumin; Kim, Jonggi; Lee, Sunghoon; Lim, Dong Hyeok; Cho, Mann Ho; Sohn, Hyunchul.

In: Microelectronic Engineering, Vol. 110, 27.05.2013, p. 6-11.

Research output: Contribution to journalArticle

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AU - Cho, Mann Ho

AU - Sohn, Hyunchul

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