Effective fixed-point pipelined divider for mobile rendering processors

Woo Chan Park, Jun Hyun Bae, Jinhong Park, Tack-Don Han, Yong Jin Park

Research output: Contribution to journalArticle

Abstract

In this paper, we proposed that an area- and speedeffective fixed-point pipelined divider be used for reducing the bit-width of a division unit to fit a mobile rendering processor. To decide the bit-width of a division unit, error analysis has been carried out in various ways. As a result, when the original bit-width was 31-bit, the proposed method reduced the bit-width to 24-bit and reduced the area by 42% with a maximum error of 0.00001%.

Original languageEnglish
Pages (from-to)1443-1448
Number of pages6
JournalIEICE Transactions on Information and Systems
VolumeE96-D
Issue number7
DOIs
Publication statusPublished - 2013 Jan 1

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Error analysis

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

Cite this

Park, Woo Chan ; Bae, Jun Hyun ; Park, Jinhong ; Han, Tack-Don ; Park, Yong Jin. / Effective fixed-point pipelined divider for mobile rendering processors. In: IEICE Transactions on Information and Systems. 2013 ; Vol. E96-D, No. 7. pp. 1443-1448.
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Effective fixed-point pipelined divider for mobile rendering processors. / Park, Woo Chan; Bae, Jun Hyun; Park, Jinhong; Han, Tack-Don; Park, Yong Jin.

In: IEICE Transactions on Information and Systems, Vol. E96-D, No. 7, 01.01.2013, p. 1443-1448.

Research output: Contribution to journalArticle

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