Effective memory-processor integrated architecture for computer vision

Research output: Contribution to journalConference article

5 Citations (Scopus)

Abstract

In this paper an effective memory-processor integrated architecture, called memory_based processor array (MPA), for computer vision is proposed. The MPA can be easily attached into any host system via memory interface. In order to measure the impact of the memory interface structure an analytical model is derived. The performance improvement on the proposed model for the memory interface architecture of the MPA system can be 6% to approximately 40% for vision tasks consisting of sequential and data parallel tasks. The asymptotic time complexities of the mapping algorithms are evaluated to verify the cost-effectiveness and the efficiency of the MPA system.

Original languageEnglish
Pages (from-to)266-269
Number of pages4
JournalProceedings of the International Conference on Parallel Processing
Publication statusPublished - 1997 Jan 1
EventProceedings of the 1997 International Conference on Parallel Processing - Bloomington, IL, USA
Duration: 1997 Sep 111997 Sep 15

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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