The memory cell density and memory capacity have been increased for obtaining larger and faster memory. However, this threatens the memory reliability by increasing the probability of faulty cell generation. In this paper, a fast and small-area built-in redundancy analysis (RA) for the post-bond repair process in 3D memory is proposed. Spare line allocation is the structure for memory repair which the most widely used. However, the spare line structure that replaces the entire line which contains faults in each memory layer occurs inefficiency in repairing a small number of faults, including single faults, and it is difficult to share spares between layers. The proposed idea is to use spare line to repair line faults according to the characteristics of it, and to complement the structural limitations by proposing a new redundant spare. This is base common spare located on the base die, and it can be shared across all layers. The proposed BIRA improves the efficiency of spare lines with two complementary spare resource structures, achieving a short repair time and high repair rate. The proposed BIRA achieves 100% repair rate when there are at least 2 times more faults than the previous works with the same hardware overhead. In addition, it takes only at most 80% of the analysis time compared to the previous works, and as the number of faults increases, the analysis time reduction becomes greater compared to the previous works.
|Number of pages||14|
|Publication status||Published - 2021|
Bibliographical notePublisher Copyright:
© 2013 IEEE.
All Science Journal Classification (ASJC) codes
- Computer Science(all)
- Materials Science(all)