Effects of channel thickness variation on bias stress instability of InGaZnO thin-film transistors

Edward Namkyu Cho, Jung Han Kang, Ilgu Yun

Research output: Contribution to journalArticle

41 Citations (Scopus)

Abstract

Here, we report on the effects of channel (or active) layer thickness on the bias stress instability of InGaZnO (IGZO) thin-film transistors (TFTs). The investigation on variations of TFT characteristics under the electrical bias stress is very crucial for commercial applications. In this work, the initial electrical characteristics of the tested TFTs with different channel layer thicknesses (40, 50, and 60 nm) are performed. Various gate bias (V GS) stresses (10, 20, and 30 V) are then applied to the tested TFTs. For all VGS stresses with different channel layer thickness, the experimentally measured threshold voltage shift (ΔVth) as a function of stress time is precisely modeled with stretched-exponential function. It is indicated that the ΔVth is generated by carrier trapping but not defect creation. It is also observed that the ΔV th shows incremental behavior as the channel layer thickness increases. Thus, it is verified that the increase of total trap states (N T) and free carriers resulted in the increase of ΔV th as the channel layer thickness increases.

Original languageEnglish
Pages (from-to)1792-1795
Number of pages4
JournalMicroelectronics Reliability
Volume51
Issue number9-11
DOIs
Publication statusPublished - 2011 Sep 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Safety, Risk, Reliability and Quality
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

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