The effects of TaN Cu diffusion barrier in Cu-gate ZnO:N thin-film transistors (TFTs) were studied. Bias stress tests were performed on Cu-gate TFTs with atomic layer deposited Al2O3 and HfO2 gate insulators. The mobility, the threshold voltage, and the reliability were significantly improved by applying a TaN diffusion barrier at the interface between the Cu gate and the gate insulator. The reduction in Cu diffusion by the diffusion barrier is a key process that increases device stability and results in improved oxide TFT performance.
Bibliographical noteFunding Information:
This work was supported in part by a National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIP) (NRF-2014R1A2A1A11052588), in part by the Korea Evaluation Institute of Industrial Technology (KEIT) funded by the Ministry of Trade, Industry, and Energy (MOTIE) (Project 10050296, Large scale (Over 8") synthesis and evaluation technology of 2-dimensional chalcogenides for next generation electronic devices), in part by Samsung Display CO., LTD., in part by the Center for Integrated Smart Sensors funded by the Ministry of Science, ICT & Future Planning as Global Frontier Project. (CISS-2011-0031848), and in part by the Industrial Strategic Technology Development Program (10041926, Development of high density plasma technologies for thin film deposition of nanoscale semiconductors and flexible display processing) funded by the Ministry of Knowledge Economy (MKE, Korea).
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering