Effects of type and density of interface trap in tunneling oxide for flash memory devices

Jun Yeong Lim, Pyung Moon, Ilgu Yun

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As the device size in the chip shrinks, shrinking the size of the insulators including tunneling oxide and the inter-poly dielectric is mainly focused on the memory devices. However, the degradation of reliability of insulators is also induced as decreasing the size of chip. In case of flash memory, especially, operation principle is cycling of electrons between floating gate and substrate. So, the degradation is easily caused by the traps caused by tunneling at interface and generation of leakage path through tunneling oxide as scaling down. In this paper, the effects of the trap density and the type of trap at the interface in tunneling oxide are analyzed by using the change of the simulated current density through the tunneling oxide using TCAD model.

Original languageEnglish
Title of host publication2012 IEEE International Conference on Electron Devices and Solid State Circuit, EDSSC 2012
DOIs
Publication statusPublished - 2012
Event2012 8th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2012 - Bangkok, Thailand
Duration: 2012 Dec 32012 Dec 5

Publication series

Name2012 IEEE International Conference on Electron Devices and Solid State Circuit, EDSSC 2012

Other

Other2012 8th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2012
CountryThailand
CityBangkok
Period12/12/312/12/5

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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