In the recent ATM Forum activities, considerable efforts have been focused on the available bit rate (ABR) service, which enables maximal link utilisation in the ATM network. An ABR service engine is presented, which provides optimal hardware solution for all functions of the ABR service algorithm. To compute congestion control information, the ABR service engine consists of an ER engine, a queueing connection (QC) estimation unit, and a cell decoder/encoder (CDE). To implement the algorithm efficiently, the new engine uses the following schemes. The ER is periodically computed in order to provide sufficient computation time. Through a periodical computation, a low cell delay is achieved when cells pass through the ABR service engine. Using a QC corrector, the implementation of the QC estimation unit is simplified. A register control block efficiently controls internal variables, and arithmetic units are designed for precise computation with simple architecture. Therefore, the ABR service engine is very small in size and provides high speed. In addition, it realises the computation of the congestion control information without a cell delay.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering