Efficient design of symbol detector for MIMO-OFDM based wireless LANs

Noh Seungpyo, Jung Yunho, Kim Jaeseok

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, an efficient hardware architecture for MEMO-OFDM symbol detector with two transmit and two receive antennas is proposed. The proposed symbol detector supports two MEMO-OFDM modes of SFBC-OFDM and SDM-OFDM. It can be implemented with shared-architecture, since the detection algorithms of two MIMO-OFDM modes are similar. Therefore, by eliminating duplicated function blocks, reduced-complexity implementation can be possible. It was designed in a hardware description language and synthesized to gate-level circuits using 0.18um CMOS standard cell library. The total logic gate count for the symbol detector is 164K. By the efficient hardware architecture, the proposed symbol detector results in the reduction of the logic gates by 34% and the power consumption by 38%.

Original languageEnglish
Title of host publicationSiPS 2005
Subtitle of host publicationIEEE Workshop on Signal Processing Systems - Design and Implementation, Proceedings
Pages25-29
Number of pages5
Volume2005
DOIs
Publication statusPublished - 2005 Dec 1
EventSiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation - Athens, Greece
Duration: 2005 Nov 22005 Nov 4

Other

OtherSiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation
CountryGreece
CityAthens
Period05/11/205/11/4

All Science Journal Classification (ASJC) codes

  • Media Technology
  • Signal Processing

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    Seungpyo, N., Yunho, J., & Jaeseok, K. (2005). Efficient design of symbol detector for MIMO-OFDM based wireless LANs. In SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation, Proceedings (Vol. 2005, pp. 25-29). [1579833] https://doi.org/10.1109/SIPS.2005.1579833