Efficient function mapping in nanoscale crossbar architecture

Joon Sung Yang, Rudrajit Datta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

Nanoscale crossbar architectures have been proposed as viable alternatives for overcoming the fundamental physical limitations of CMOS technology. However due to the manufacturing processes for nanofabrication and their smaller feature sizes, defect densities are higher. This paper presents an efficient function mapping method in the presence of high defect rates for nanoscale crossbar arrays. Given a function and a defect map that describes fault patterns in the crossbar architecture, the approach described here tries to find a valid function mapping, if one exists, using a matrix representation. A set of constraints are derived to preserve semantics and then Integer Linear Programming (ILP) is used to solve the equations. Experimental results show the proposed approach provides efficient utilization of nanoscale crossbars in mapping functions in presence of high defect rates.

Original languageEnglish
Title of host publicationProceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011
Pages190-196
Number of pages7
DOIs
Publication statusPublished - 2011 Dec 1
Event2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011 - Vancouver, BC, Canada
Duration: 2011 Oct 32011 Oct 5

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)1550-5774

Conference

Conference2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011
CountryCanada
CityVancouver, BC
Period11/10/311/10/5

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Yang, J. S., & Datta, R. (2011). Efficient function mapping in nanoscale crossbar architecture. In Proceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011 (pp. 190-196). [6104443] (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFT.2011.39