Efficient function mapping in nanoscale crossbar architecture

Joon Sung Yang; Rudrajit Datta

doi:10.1109/DFT.2011.39

Efficient function mapping in nanoscale crossbar architecture

Joon Sung Yang, Rudrajit Datta

College of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Citations (Scopus)

Abstract

Nanoscale crossbar architectures have been proposed as viable alternatives for overcoming the fundamental physical limitations of CMOS technology. However due to the manufacturing processes for nanofabrication and their smaller feature sizes, defect densities are higher. This paper presents an efficient function mapping method in the presence of high defect rates for nanoscale crossbar arrays. Given a function and a defect map that describes fault patterns in the crossbar architecture, the approach described here tries to find a valid function mapping, if one exists, using a matrix representation. A set of constraints are derived to preserve semantics and then Integer Linear Programming (ILP) is used to solve the equations. Experimental results show the proposed approach provides efficient utilization of nanoscale crossbars in mapping functions in presence of high defect rates.

Original language	English
Title of host publication	Proceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011
Pages	190-196
Number of pages	7
DOIs	https://doi.org/10.1109/DFT.2011.39
Publication status	Published - 2011
Event	2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011 - Vancouver, BC, Canada Duration: 2011 Oct 3 → 2011 Oct 5

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)	1550-5774

Conference

Conference	2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011
Country/Territory	Canada
City	Vancouver, BC
Period	11/10/3 → 11/10/5

All Science Journal Classification (ASJC) codes

Engineering(all)

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10.1109/DFT.2011.39

Cite this

Yang, J. S., & Datta, R. (2011). Efficient function mapping in nanoscale crossbar architecture. In Proceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011 (pp. 190-196). [6104443] (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFT.2011.39

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title = "Efficient function mapping in nanoscale crossbar architecture",

abstract = "Nanoscale crossbar architectures have been proposed as viable alternatives for overcoming the fundamental physical limitations of CMOS technology. However due to the manufacturing processes for nanofabrication and their smaller feature sizes, defect densities are higher. This paper presents an efficient function mapping method in the presence of high defect rates for nanoscale crossbar arrays. Given a function and a defect map that describes fault patterns in the crossbar architecture, the approach described here tries to find a valid function mapping, if one exists, using a matrix representation. A set of constraints are derived to preserve semantics and then Integer Linear Programming (ILP) is used to solve the equations. Experimental results show the proposed approach provides efficient utilization of nanoscale crossbars in mapping functions in presence of high defect rates.",

author = "Yang, {Joon Sung} and Rudrajit Datta",

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doi = "10.1109/DFT.2011.39",

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series = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",

pages = "190--196",

booktitle = "Proceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011",

note = "2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011 ; Conference date: 03-10-2011 Through 05-10-2011",

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Yang, JS & Datta, R 2011, Efficient function mapping in nanoscale crossbar architecture. in Proceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011., 6104443, Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 190-196, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, 11/10/3. https://doi.org/10.1109/DFT.2011.39

Efficient function mapping in nanoscale crossbar architecture. / Yang, Joon Sung; Datta, Rudrajit.

Proceedings - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011. 2011. p. 190-196 6104443 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - Nanoscale crossbar architectures have been proposed as viable alternatives for overcoming the fundamental physical limitations of CMOS technology. However due to the manufacturing processes for nanofabrication and their smaller feature sizes, defect densities are higher. This paper presents an efficient function mapping method in the presence of high defect rates for nanoscale crossbar arrays. Given a function and a defect map that describes fault patterns in the crossbar architecture, the approach described here tries to find a valid function mapping, if one exists, using a matrix representation. A set of constraints are derived to preserve semantics and then Integer Linear Programming (ILP) is used to solve the equations. Experimental results show the proposed approach provides efficient utilization of nanoscale crossbars in mapping functions in presence of high defect rates.

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Efficient function mapping in nanoscale crossbar architecture

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