Efficient Hardware Implementation of STDP for AER Based Large-Scale SNN Neuromorphic System

Jaeyoon Kim, Jia Park, Sunghwan Joo, Seong Ook Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a novel method to reduce the hardware cost for implementing spike-timing-dependent- plasticity (STDP) by eliminating the unnecessary decoding processes and using the addresses directly from the AER in the spiking neuron network (SNN) neuromorphic processor. Although SNN has the advantage of operating in low power, the major bottleneck in large scale SNN neuromorphic systems is the high hardware cost due to complex neuron dynamics. In SNN, STDP learning rule is usually implemented by the shift registers to record the spike history. Thus, as the number of neurons increases, the number of shift registers must increase accordingly. Moreover, large scale SNN neuromorphic systems lack the capability to process various inputs at once, thus rely on address event representation to send the addresses with the spikes and decode this information again for STDP learning. We implemented a STDP circuit for SNN system comprising 784 inputs and 256 outputs for MNIST image recognition on a Xilinx KCU 105 FPGA board. The proposed STDP circuit showed a 80% reduction in LUT, 88% in FF, and 83% in power compared to the conventional STDP circuit.

Original languageEnglish
Title of host publicationITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages411-415
Number of pages5
ISBN (Electronic)9784885523281
Publication statusPublished - 2020 Jul
Event35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020 - Nagoya, Japan
Duration: 2020 Jul 32020 Jul 6

Publication series

NameITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications

Conference

Conference35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020
CountryJapan
CityNagoya
Period20/7/320/7/6

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Information Systems and Management
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Efficient Hardware Implementation of STDP for AER Based Large-Scale SNN Neuromorphic System'. Together they form a unique fingerprint.

  • Cite this

    Kim, J., Park, J., Joo, S., & Jung, S. O. (2020). Efficient Hardware Implementation of STDP for AER Based Large-Scale SNN Neuromorphic System. In ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications (pp. 411-415). [9183346] (ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications). Institute of Electrical and Electronics Engineers Inc..