This paper proposes a novel method to reduce the hardware cost for implementing spike-timing-dependent- plasticity (STDP) by eliminating the unnecessary decoding processes and using the addresses directly from the AER in the spiking neuron network (SNN) neuromorphic processor. Although SNN has the advantage of operating in low power, the major bottleneck in large scale SNN neuromorphic systems is the high hardware cost due to complex neuron dynamics. In SNN, STDP learning rule is usually implemented by the shift registers to record the spike history. Thus, as the number of neurons increases, the number of shift registers must increase accordingly. Moreover, large scale SNN neuromorphic systems lack the capability to process various inputs at once, thus rely on address event representation to send the addresses with the spikes and decode this information again for STDP learning. We implemented a STDP circuit for SNN system comprising 784 inputs and 256 outputs for MNIST image recognition on a Xilinx KCU 105 FPGA board. The proposed STDP circuit showed a 80% reduction in LUT, 88% in FF, and 83% in power compared to the conventional STDP circuit.