Efficient Low-Latency Implementation of CORDIC-Based Sorted QR Decomposition for Multi-Gbps MIMO Systems

Hyukyeon Lee; Kyungmook Oh; Minjeong Cho; Yunseok Jang; Jaeseok Kim

doi:10.1109/TCSII.2018.2853099

Efficient Low-Latency Implementation of CORDIC-Based Sorted QR Decomposition for Multi-Gbps MIMO Systems

Hyukyeon Lee, Kyungmook Oh, Minjeong Cho, Yunseok Jang, Jaeseok Kim

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

This brief presents the efficient VLSI implementation of coordinate rotation digital computer (CORDIC)-based sorted QR decomposition (SQRD) for multiple-input and multiple-output (MIMO) systems. SQRD is widely adopted in MIMO signal processing to mitigate error propagation. However, its iterative sorting process after every column annihilation requires a large hardware overhead and suffers from a latency issue. The proposed CORDIC-based SQRD modifies a real-value decomposition matrix to utilize symmetry and jointly performs sorting processes and CORDIC rotations with adjacent symmetric columns to reduce the required number of CORDIC rotations and CORDIC stages. Furthermore, the VLSI design of the proposed SQRD has been synthesized and implemented with a Virtex-6 FPGA and a 65-nm CMOS technology, respectively. The 65-nm implementation results show an overall processing latency of 266.5 ns, a throughput of 48.8 MSQRD per second, and can support a 4.7-Gbps MIMO system throughput.

Original language	English
Article number	8404092
Pages (from-to)	1375-1379
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	65
Issue number	10
DOIs	https://doi.org/10.1109/TCSII.2018.2853099
Publication status	Published - 2018 Oct

Bibliographical note

Funding Information:
Manuscript received June 19, 2018; accepted June 27, 2018. Date of publication July 5, 2018; date of current version September 27, 2018. This work was supported in part by a National Research Foundation of Korea grant funded by the Korea Government under Grant NRF-2015R1A2A2A01004883, and in part by the System LSI Division of Samsung Electronics Company, Ltd. This brief was recommended by Associate Editor J. M. de la Rosa. (Corresponding author: Jaeseok Kim.) The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: jaekim@yonsei.ac.kr). Digital Object Identifier 10.1109/TCSII.2018.2853099

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TCSII.2018.2853099

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abstract = "This brief presents the efficient VLSI implementation of coordinate rotation digital computer (CORDIC)-based sorted QR decomposition (SQRD) for multiple-input and multiple-output (MIMO) systems. SQRD is widely adopted in MIMO signal processing to mitigate error propagation. However, its iterative sorting process after every column annihilation requires a large hardware overhead and suffers from a latency issue. The proposed CORDIC-based SQRD modifies a real-value decomposition matrix to utilize symmetry and jointly performs sorting processes and CORDIC rotations with adjacent symmetric columns to reduce the required number of CORDIC rotations and CORDIC stages. Furthermore, the VLSI design of the proposed SQRD has been synthesized and implemented with a Virtex-6 FPGA and a 65-nm CMOS technology, respectively. The 65-nm implementation results show an overall processing latency of 266.5 ns, a throughput of 48.8 MSQRD per second, and can support a 4.7-Gbps MIMO system throughput.",

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note = "Funding Information: Manuscript received June 19, 2018; accepted June 27, 2018. Date of publication July 5, 2018; date of current version September 27, 2018. This work was supported in part by a National Research Foundation of Korea grant funded by the Korea Government under Grant NRF-2015R1A2A2A01004883, and in part by the System LSI Division of Samsung Electronics Company, Ltd. This brief was recommended by Associate Editor J. M. de la Rosa. (Corresponding author: Jaeseok Kim.) The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: jaekim@yonsei.ac.kr). Digital Object Identifier 10.1109/TCSII.2018.2853099 Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

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Efficient Low-Latency Implementation of CORDIC-Based Sorted QR Decomposition for Multi-Gbps MIMO Systems

Abstract

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