This brief presents the efficient VLSI implementation of coordinate rotation digital computer (CORDIC)-based sorted QR decomposition (SQRD) for multiple-input and multiple-output (MIMO) systems. SQRD is widely adopted in MIMO signal processing to mitigate error propagation. However, its iterative sorting process after every column annihilation requires a large hardware overhead and suffers from a latency issue. The proposed CORDIC-based SQRD modifies a real-value decomposition matrix to utilize symmetry and jointly performs sorting processes and CORDIC rotations with adjacent symmetric columns to reduce the required number of CORDIC rotations and CORDIC stages. Furthermore, the VLSI design of the proposed SQRD has been synthesized and implemented with a Virtex-6 FPGA and a 65-nm CMOS technology, respectively. The 65-nm implementation results show an overall processing latency of 266.5 ns, a throughput of 48.8 MSQRD per second, and can support a 4.7-Gbps MIMO system throughput.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2018 Oct|
Bibliographical noteFunding Information:
Manuscript received June 19, 2018; accepted June 27, 2018. Date of publication July 5, 2018; date of current version September 27, 2018. This work was supported in part by a National Research Foundation of Korea grant funded by the Korea Government under Grant NRF-2015R1A2A2A01004883, and in part by the System LSI Division of Samsung Electronics Company, Ltd. This brief was recommended by Associate Editor J. M. de la Rosa. (Corresponding author: Jaeseok Kim.) The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: firstname.lastname@example.org). Digital Object Identifier 10.1109/TCSII.2018.2853099
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering