Efficient method of partitioning circuits for multiple FPGA implementation

Nam Sung Woo, Jaeseok Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)

Abstract

We developed a new method called MP2, for partitioning networks into multiple (>2) blocks each of which has both size and pin constraints. The MP2 method uses an improvement approach and tries to minimize the total number of terminals of all blocks while satisfying the pin and size constraints of every block. It supports multiple classes of cells in input networks and blocks. It makes use of a scalar value of benefit which captures lookahead information. It is the first improvement method that considers pin constraints of blocks. It has been applied to partitioning technology-mapped circuits into multiple FPGA chips. In addition to describing the MP2 method, we will discuss some interesting findings we gleaned during our experiments.

Original languageEnglish
Title of host publicationProceedings - Design Automation Conference
PublisherPubl by IEEE
Pages202-207
Number of pages6
ISBN (Print)0897915771, 9780897915779
DOIs
Publication statusPublished - 1993
EventProceedings of the 30th ACM/IEEE Design Automation Conference - Dallas, TX, USA
Duration: 1993 Jun 141993 Jun 18

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0146-7123

Conference

ConferenceProceedings of the 30th ACM/IEEE Design Automation Conference
CityDallas, TX, USA
Period93/6/1493/6/18

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Woo, N. S., & Kim, J. (1993). Efficient method of partitioning circuits for multiple FPGA implementation. In Proceedings - Design Automation Conference (pp. 202-207). (Proceedings - Design Automation Conference). Publ by IEEE. https://doi.org/10.1145/157485.164669