Efficient multi-site testing using ate channel sharing

Kyoung Woon Eom, Dong Kwan Han, Yong Lee, Hak Song Kim, Sungho Kang

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Multi-site testing is considered as a solution to reduce test costs. This paper presents a new channel sharing architecture that enables I/O pins to share automatic test equipment (ATE) channels using simple circuitry such as tri-state buffers, AND gates, and multiple-input signature registers (MISR). The main advantage of the proposed architecture is that it is implemented on probe cards and does not require any additional circuitry on a target device under test (DUT). In addition, the proposed architecture can perform DC parametric testing of the DUT such as leakage testing, even if the different DUTs share the same ATE channels. The simulation results show that the proposed architecture is very efficient and is applicable to both wafer testing and package testing.

Original languageEnglish
Pages (from-to)259-262
Number of pages4
JournalJournal of Semiconductor Technology and Science
Volume13
Issue number3
DOIs
Publication statusPublished - 2013 Jun 1

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Testing
Buffers
Costs

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Eom, Kyoung Woon ; Han, Dong Kwan ; Lee, Yong ; Kim, Hak Song ; Kang, Sungho. / Efficient multi-site testing using ate channel sharing. In: Journal of Semiconductor Technology and Science. 2013 ; Vol. 13, No. 3. pp. 259-262.
@article{c3c3d7c53eee448daaa98cb4225eebbd,
title = "Efficient multi-site testing using ate channel sharing",
abstract = "Multi-site testing is considered as a solution to reduce test costs. This paper presents a new channel sharing architecture that enables I/O pins to share automatic test equipment (ATE) channels using simple circuitry such as tri-state buffers, AND gates, and multiple-input signature registers (MISR). The main advantage of the proposed architecture is that it is implemented on probe cards and does not require any additional circuitry on a target device under test (DUT). In addition, the proposed architecture can perform DC parametric testing of the DUT such as leakage testing, even if the different DUTs share the same ATE channels. The simulation results show that the proposed architecture is very efficient and is applicable to both wafer testing and package testing.",
author = "Eom, {Kyoung Woon} and Han, {Dong Kwan} and Yong Lee and Kim, {Hak Song} and Sungho Kang",
year = "2013",
month = "6",
day = "1",
doi = "10.5573/JSTS.2013.13.3.259",
language = "English",
volume = "13",
pages = "259--262",
journal = "Journal of Semiconductor Technology and Science",
issn = "1598-1657",
publisher = "Institute of Electronics Engineers of Korea",
number = "3",

}

Efficient multi-site testing using ate channel sharing. / Eom, Kyoung Woon; Han, Dong Kwan; Lee, Yong; Kim, Hak Song; Kang, Sungho.

In: Journal of Semiconductor Technology and Science, Vol. 13, No. 3, 01.06.2013, p. 259-262.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Efficient multi-site testing using ate channel sharing

AU - Eom, Kyoung Woon

AU - Han, Dong Kwan

AU - Lee, Yong

AU - Kim, Hak Song

AU - Kang, Sungho

PY - 2013/6/1

Y1 - 2013/6/1

N2 - Multi-site testing is considered as a solution to reduce test costs. This paper presents a new channel sharing architecture that enables I/O pins to share automatic test equipment (ATE) channels using simple circuitry such as tri-state buffers, AND gates, and multiple-input signature registers (MISR). The main advantage of the proposed architecture is that it is implemented on probe cards and does not require any additional circuitry on a target device under test (DUT). In addition, the proposed architecture can perform DC parametric testing of the DUT such as leakage testing, even if the different DUTs share the same ATE channels. The simulation results show that the proposed architecture is very efficient and is applicable to both wafer testing and package testing.

AB - Multi-site testing is considered as a solution to reduce test costs. This paper presents a new channel sharing architecture that enables I/O pins to share automatic test equipment (ATE) channels using simple circuitry such as tri-state buffers, AND gates, and multiple-input signature registers (MISR). The main advantage of the proposed architecture is that it is implemented on probe cards and does not require any additional circuitry on a target device under test (DUT). In addition, the proposed architecture can perform DC parametric testing of the DUT such as leakage testing, even if the different DUTs share the same ATE channels. The simulation results show that the proposed architecture is very efficient and is applicable to both wafer testing and package testing.

UR - http://www.scopus.com/inward/record.url?scp=84878855687&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84878855687&partnerID=8YFLogxK

U2 - 10.5573/JSTS.2013.13.3.259

DO - 10.5573/JSTS.2013.13.3.259

M3 - Article

VL - 13

SP - 259

EP - 262

JO - Journal of Semiconductor Technology and Science

JF - Journal of Semiconductor Technology and Science

SN - 1598-1657

IS - 3

ER -