Abstract
In spite of using scan designs, there remain problems concerning the generation and confirmation of test vectors for potential timing problems. Most fault simulators for path-delay faults rely on the use of augmented scan flip-flops to convert the timing vector problem to a purely combinational one. The paper describes an efficient path-delay fault simulation algorithm for standard scan environments. The new simulation algorithm using various new logic values is based on the parallel-pattern-single-fault-propagation technique. The experimental results show the efficiency of the new algorithm.
Original language | English |
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Pages (from-to) | 315-320 |
Number of pages | 6 |
Journal | IEE Proceedings: Circuits, Devices and Systems |
Volume | 149 |
Issue number | 5-6 |
DOIs | |
Publication status | Published - 2002 Oct |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering