Efficient path-delay fault simulation for standard scan design

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


In spite of using scan designs, there remain problems concerning the generation and confirmation of test vectors for potential timing problems. Most fault simulators for path-delay faults rely on the use of augmented scan flip-flops to convert the timing vector problem to a purely combinational one. The paper describes an efficient path-delay fault simulation algorithm for standard scan environments. The new simulation algorithm using various new logic values is based on the parallel-pattern-single-fault-propagation technique. The experimental results show the efficiency of the new algorithm.

Original languageEnglish
Pages (from-to)315-320
Number of pages6
JournalIEE Proceedings: Circuits, Devices and Systems
Issue number5-6
Publication statusPublished - 2002 Oct

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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