Abstract
In spite of using scan designs, there remain problems concerning the generation and confirmation of test vectors for potential timing problems. Most fault simulators for path-delay faults rely on the use of augmented scan flip-flops to convert the timing vector problem to a purely combinational one. The paper describes an efficient path-delay fault simulation algorithm for standard scan environments. The new simulation algorithm using various new logic values is based on the parallel-pattern-single-fault-propagation technique. The experimental results show the efficiency of the new algorithm.
| Original language | English |
|---|---|
| Pages (from-to) | 315-320 |
| Number of pages | 6 |
| Journal | IEE Proceedings: Circuits, Devices and Systems |
| Volume | 149 |
| Issue number | 5-6 |
| DOIs | |
| Publication status | Published - 2002 Oct 1 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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Efficient path-delay fault simulation for standard scan design. / Kang, Sungho.
In: IEE Proceedings: Circuits, Devices and Systems, Vol. 149, No. 5-6, 01.10.2002, p. 315-320.Research output: Contribution to journal › Article
TY - JOUR
T1 - Efficient path-delay fault simulation for standard scan design
AU - Kang, Sungho
PY - 2002/10/1
Y1 - 2002/10/1
N2 - In spite of using scan designs, there remain problems concerning the generation and confirmation of test vectors for potential timing problems. Most fault simulators for path-delay faults rely on the use of augmented scan flip-flops to convert the timing vector problem to a purely combinational one. The paper describes an efficient path-delay fault simulation algorithm for standard scan environments. The new simulation algorithm using various new logic values is based on the parallel-pattern-single-fault-propagation technique. The experimental results show the efficiency of the new algorithm.
AB - In spite of using scan designs, there remain problems concerning the generation and confirmation of test vectors for potential timing problems. Most fault simulators for path-delay faults rely on the use of augmented scan flip-flops to convert the timing vector problem to a purely combinational one. The paper describes an efficient path-delay fault simulation algorithm for standard scan environments. The new simulation algorithm using various new logic values is based on the parallel-pattern-single-fault-propagation technique. The experimental results show the efficiency of the new algorithm.
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U2 - 10.1049/ip-cds:20020496
DO - 10.1049/ip-cds:20020496
M3 - Article
AN - SCOPUS:0036823017
VL - 149
SP - 315
EP - 320
JO - IET Circuits, Devices and Systems
JF - IET Circuits, Devices and Systems
SN - 1751-858X
IS - 5-6
ER -