In spite of using scan designs, there remain problems concerning the generation and confirmation of test vectors for potential timing problems. Most fault simulators for path-delay faults rely on the use of augmented scan flip-flops to convert the timing vector problem to a purely combinational one. The paper describes an efficient path-delay fault simulation algorithm for standard scan environments. The new simulation algorithm using various new logic values is based on the parallel-pattern-single-fault-propagation technique. The experimental results show the efficiency of the new algorithm.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering