This paper describes a path delay fault simulator for standard scan environments and introduces a new algorithm using new logic values in order to enlarge the scope of a path delay fault simulation to the CMOS designs. A new simulator can deal with mixed level circuits. Considering switch level devices, this simulator can treat delay faults more closely to their electrical behavior. The results prove the efficiency of the simulator.
|Number of pages||4|
|Journal||Proceedings of the Annual IEEE International ASIC Conference and Exhibit|
|Publication status||Published - 1996|
|Event||Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA|
Duration: 1996 Sep 23 → 1996 Sep 27
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering