Efficient path-delay fault simulator for mixed level circuits

Yong Seok Kang, Yong Tae Yim, Sungho Kang

Research output: Contribution to journalConference article

Abstract

This paper describes a path delay fault simulator for standard scan environments and introduces a new algorithm using new logic values in order to enlarge the scope of a path delay fault simulation to the CMOS designs. A new simulator can deal with mixed level circuits. Considering switch level devices, this simulator can treat delay faults more closely to their electrical behavior. The results prove the efficiency of the simulator.

Original languageEnglish
Pages (from-to)263-266
Number of pages4
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
Publication statusPublished - 1996
EventProceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA
Duration: 1996 Sep 231996 Sep 27

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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