Efficient path delay test generation for custom designs

Sungho Kang, Bill Underwood, Wai On Law, Haluk Konuk

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.

Original languageEnglish
Pages (from-to)138-149
Number of pages12
JournalETRI Journal
Volume23
Issue number3
Publication statusPublished - 2001 Sep 1

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Networks (circuits)
VLSI circuits
Intellectual property
Testing

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Computer Science(all)
  • Electrical and Electronic Engineering

Cite this

Kang, S., Underwood, B., Law, W. O., & Konuk, H. (2001). Efficient path delay test generation for custom designs. ETRI Journal, 23(3), 138-149.
Kang, Sungho ; Underwood, Bill ; Law, Wai On ; Konuk, Haluk. / Efficient path delay test generation for custom designs. In: ETRI Journal. 2001 ; Vol. 23, No. 3. pp. 138-149.
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Kang, S, Underwood, B, Law, WO & Konuk, H 2001, 'Efficient path delay test generation for custom designs', ETRI Journal, vol. 23, no. 3, pp. 138-149.

Efficient path delay test generation for custom designs. / Kang, Sungho; Underwood, Bill; Law, Wai On; Konuk, Haluk.

In: ETRI Journal, Vol. 23, No. 3, 01.09.2001, p. 138-149.

Research output: Contribution to journalArticle

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Kang S, Underwood B, Law WO, Konuk H. Efficient path delay test generation for custom designs. ETRI Journal. 2001 Sep 1;23(3):138-149.