Abstract
Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.
| Original language | English |
|---|---|
| Pages (from-to) | 138-149 |
| Number of pages | 12 |
| Journal | ETRI Journal |
| Volume | 23 |
| Issue number | 3 |
| Publication status | Published - 2001 Sep 1 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Computer Science(all)
- Electrical and Electronic Engineering
Cite this
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Efficient path delay test generation for custom designs. / Kang, Sungho; Underwood, Bill; Law, Wai On; Konuk, Haluk.
In: ETRI Journal, Vol. 23, No. 3, 01.09.2001, p. 138-149.Research output: Contribution to journal › Article
TY - JOUR
T1 - Efficient path delay test generation for custom designs
AU - Kang, Sungho
AU - Underwood, Bill
AU - Law, Wai On
AU - Konuk, Haluk
PY - 2001/9/1
Y1 - 2001/9/1
N2 - Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.
AB - Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.
UR - http://www.scopus.com/inward/record.url?scp=0035447323&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0035447323&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0035447323
VL - 23
SP - 138
EP - 149
JO - ETRI Journal
JF - ETRI Journal
SN - 1225-6463
IS - 3
ER -