Efficient path delay testing using scan justification

Kyung Hoi Huh, Yong Seok Kang, Sungho Kang

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45% over the conventional functional justification.

Original languageEnglish
Pages (from-to)187-194
Number of pages8
JournalETRI Journal
Volume25
Issue number3
DOIs
Publication statusPublished - 2003 Jan 1

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Combinatorial circuits
Networks (circuits)
Flip flop circuits
Digital circuits
Testing

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Computer Science(all)
  • Electrical and Electronic Engineering

Cite this

Huh, Kyung Hoi ; Kang, Yong Seok ; Kang, Sungho. / Efficient path delay testing using scan justification. In: ETRI Journal. 2003 ; Vol. 25, No. 3. pp. 187-194.
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Efficient path delay testing using scan justification. / Huh, Kyung Hoi; Kang, Yong Seok; Kang, Sungho.

In: ETRI Journal, Vol. 25, No. 3, 01.01.2003, p. 187-194.

Research output: Contribution to journalArticle

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