Efficient systolic-array redundancy architecture for offline/online repair

Keewon Cho, Ingeol Lee, Hyeonchan Lim, Sungho Kang

Research output: Contribution to journalArticle

Abstract

Neural-network computing has revolutionized the field of machine learning. The systolicarray architecture is a widely used architecture for neural-network computing acceleration that was adopted by Google in its Tensor Processing Unit (TPU). To ensure the correct operation of the neural network, the reliability of the systolic-array architecture should be guaranteed. This paper proposes an efficient systolic-array redundancy architecture that is based on systolic-array partitioning and rearranging connections of the systolic-array elements. The proposed architecture allows both offline and online repair with an extended redundancy architecture and programmable fuses and can ensure reliability even in an online situation, for which the previous fault-tolerant schemes have not been considered.

Original languageEnglish
Article number338
JournalElectronics (Switzerland)
Volume9
Issue number2
DOIs
Publication statusPublished - 2020 Feb

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Signal Processing
  • Hardware and Architecture
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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