Abstract
Neural-network computing has revolutionized the field of machine learning. The systolicarray architecture is a widely used architecture for neural-network computing acceleration that was adopted by Google in its Tensor Processing Unit (TPU). To ensure the correct operation of the neural network, the reliability of the systolic-array architecture should be guaranteed. This paper proposes an efficient systolic-array redundancy architecture that is based on systolic-array partitioning and rearranging connections of the systolic-array elements. The proposed architecture allows both offline and online repair with an extended redundancy architecture and programmable fuses and can ensure reliability even in an online situation, for which the previous fault-tolerant schemes have not been considered.
| Original language | English |
|---|---|
| Article number | 338 |
| Journal | Electronics (Switzerland) |
| Volume | 9 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 2020 Feb |
Bibliographical note
Funding Information:validation, K.C., I.L., and H.L.; formal analysis, I.L.; investigation, K.C. and H.L.; resources, K.C.; data curation, K.C.; writing—original draft preparation, K.C. and I.L.; writing—review and editing, K.C. and S.K.; visualization, K.C. and I.L.; supervision, S.K.; project administration, S.K.; funding acquisition, S.K. All authors have read and agreed to the published version of the manuscript. agreed to the published version of the manuscript. Funding: This work was supported by Samsung Electronics Company, Ltd., Hwaseong, Korea. Funding: This work was supported by Samsung Electronics Company, Ltd., Hwaseong, Korea. Conflicts of Interest: The authors declare no conflict of interest. Conflicts of Interest: The authors declare no conflict of interest.
All Science Journal Classification (ASJC) codes
- Control and Systems Engineering
- Signal Processing
- Hardware and Architecture
- Computer Networks and Communications
- Electrical and Electronic Engineering