Electrical analysis of bottom gate TFT with novel process architecture

Sang Hoon Pak, Tae Hoon Jeong, Si Joon Kim, Kyung Ho Kim, Hyun Jae Kim

Research output: Contribution to journalArticle

Abstract

Bottom gate thin film transistors (TFTs) with microcrystalline and amorphous Si (a-Si) double active layers (DAL) were fabricated. Since the process of DAL TFTs can use that of conventional a-Si TFTs, these DAL TFT process has advantages, such as low cost, large substrate, and mass production capacity. In order to analyze the degradation characteristics in saturation region for driving TFTs of active matrix organic light emitting diode, three different dynamic stresses were applied to DAL TFTs and a-Si TFTs. The threshold voltage shift of DAL TFTs and a-Si TFTs during 10,000 second stress is 0.3V and 2V, respectively. DAL TFTs were more reliable than a-Si TFTs.

Original languageEnglish
Pages (from-to)5-8
Number of pages4
JournalJournal of Information Display
Volume9
Issue number2
DOIs
Publication statusPublished - 2008 Jan 1

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Electrical and Electronic Engineering

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