Embedded-IC package using Si-interposer for mmWave Applications

In this study, we optimized the interconnection of a Si-embedded IC package using a dummy IC that includes a transmission line. We also propose an improved process method to minimize the insulator effect on the chip for W-band applications. The 30-μm-thick insulator (ϵr = 3.2) covering the dummy IC increases the ϵeff by about 5.6%, and the reflection loss is increased by 5 dB or more. In the improved process, the insulator on the circuit area is removed by using a photosensitive material (WPR-1201). In the structure, the phase difference is improved by about 5% compared to the existing process, and there is little effect of reflection loss. The analyzed chip-to-chip (CTC) interconnection with a length of 320 μm was designed with a grounded coplanar waveguide (G-CPW), and the line width was optimized for the dielectric constant and substrate height by EM simulation. All parasitic resonances, such as cavity resonance or slot loop resonance that can occur in the embedding package were analyzed using an EM simulator and circuit model. Each resonance is removed by the appropriate positioning of via holes. As a result, the measured insertion loss of the CTC interconnection is 0.2 dB at 100 GHz without degradation of return loss and the return loss is more than 18 dB at broadband (0-100 GHz). To demonstrate the technology, an embedded IC module combining an 8x frequency multiplier and the drive amplifier was realized using the proposed process. The measured peak conversion gain was improved from 2.08 to 4.6 dB at 84 GHz in comparison to the typical embedded-IC module.