Abstract
We investigate runtime environment characteristics and explore the challenges of conventional in-memory graph processing. This system-level analysis includes empirical results and observations, which are opposite to the existing expectations of graph application users. Specifically, since raw graph data are not the same as the in-memory graph data, processing a billion-scale graph exhausts all system resources and makes the target system unavailable due to out-of-memory at runtime.To address a lack of memory space problem for big-scale graph analysis, we configure real persistent memory devices (PMEMs) with different operation modes and system software frameworks. In this work, we introduce PMEM to a representative in-memory graph system, Ligra, and perform an in-depth analysis uncovering the performance behaviors of different PMEM-applied in-memory graph systems. Based on our observations, we modify Ligra to improve the graph processing performance with a solid level of data persistence. Our evaluation results reveal that Ligra, with our simple modification, exhibits 4.41× and 3.01× better performance than the original Ligra running on a virtual memory expansion and conventional persistent memory, respectively.
Original language | English |
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Title of host publication | Proceedings - 2021 IEEE 39th International Conference on Computer Design, ICCD 2021 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 316-320 |
Number of pages | 5 |
ISBN (Electronic) | 9781665432191 |
DOIs | |
Publication status | Published - 2021 |
Event | 39th IEEE International Conference on Computer Design, ICCD 2021 - Virtual, Online, United States Duration: 2021 Oct 24 → 2021 Oct 27 |
Publication series
Name | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors |
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Volume | 2021-October |
ISSN (Print) | 1063-6404 |
Conference
Conference | 39th IEEE International Conference on Computer Design, ICCD 2021 |
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Country/Territory | United States |
City | Virtual, Online |
Period | 21/10/24 → 21/10/27 |
Bibliographical note
Funding Information:VII. ACKNOWLEDGEMENT This research is mainly supported by NRF 2021R1AC4001773 and IITP 2021-0-00524. The work is also supported in part by S3RC Hynix Center, SK-Hynix (G01200477), ETRI (21ZS1300), and KAIST start-up package (G01190015). D. Park is funded by NRF 2020R1F1A1048485. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Myoungsoo Jung is the corresponding author.
Funding Information:
This research is mainly supported by NRF 2021R1AC4001773 and IITP 2021-0-00524. The work is also supported in part by S3RC Hynix Center, SKHynix (G01200477), ETRI (21ZS1300), and KAIST start-up package (G01190015). D. Park is funded by NRF 2020R1F1A1048485. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Publisher Copyright:
© 2021 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering