Abstract
Scan-based debug methods give high observability of internal signals, however, they require halting the system to scan out responses from the circuit-under-debug (CUD). This is time consuming as many scan dumps may be required. In this paper, conventional scan chains that have non-destructive scan out capability are configured to operate as multiple MISRs during system operation. Information from the multiple MISRs is monitored periodically to identify erroneous behavior. A procedure for constructing the MISRs to maximize debug capability is described. A three step process is used to zero in on the first clock cycle in which an error is present with a small number of scan dumps. Moreover, a method for bypassing errors is described to permit debug in the presence of multiple bugs.
Original language | English |
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Article number | 4641165 |
Pages (from-to) | 125-133 |
Number of pages | 9 |
Journal | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems |
DOIs | |
Publication status | Published - 2008 |
Event | 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008 - Boston, MA, United States Duration: 2008 Oct 1 → 2008 Oct 3 |
All Science Journal Classification (ASJC) codes
- Engineering(all)