Enhancing silicon debug via periodic monitoring

Joon Sung Yang; Nur A. Touba

doi:10.1109/DFT.2008.57

Enhancing silicon debug via periodic monitoring

Joon Sung Yang, Nur A. Touba

College of Engineering

Research output: Contribution to journal › Conference article

13 Citations (Scopus)

Abstract

Scan-based debug methods give high observability of internal signals, however, they require halting the system to scan out responses from the circuit-under-debug (CUD). This is time consuming as many scan dumps may be required. In this paper, conventional scan chains that have non-destructive scan out capability are configured to operate as multiple MISRs during system operation. Information from the multiple MISRs is monitored periodically to identify erroneous behavior. A procedure for constructing the MISRs to maximize debug capability is described. A three step process is used to zero in on the first clock cycle in which an error is present with a small number of scan dumps. Moreover, a method for bypassing errors is described to permit debug in the presence of multiple bugs.

Original language	English
Article number	4641165
Pages (from-to)	125-133
Number of pages	9
Journal	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
DOIs	https://doi.org/10.1109/DFT.2008.57
Publication status	Published - 2008 Dec 1
Event	23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008 - Boston, MA, United States Duration: 2008 Oct 1 → 2008 Oct 3

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1109/DFT.2008.57

Fingerprint Dive into the research topics of 'Enhancing silicon debug via periodic monitoring'. Together they form a unique fingerprint.

Cite this

Yang, J. S., & Touba, N. A. (2008). Enhancing silicon debug via periodic monitoring. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 125-133. [4641165]. https://doi.org/10.1109/DFT.2008.57

@article{79c1f1554fdd40a68598c5a5abb55cf7,

title = "Enhancing silicon debug via periodic monitoring",

abstract = "Scan-based debug methods give high observability of internal signals, however, they require halting the system to scan out responses from the circuit-under-debug (CUD). This is time consuming as many scan dumps may be required. In this paper, conventional scan chains that have non-destructive scan out capability are configured to operate as multiple MISRs during system operation. Information from the multiple MISRs is monitored periodically to identify erroneous behavior. A procedure for constructing the MISRs to maximize debug capability is described. A three step process is used to zero in on the first clock cycle in which an error is present with a small number of scan dumps. Moreover, a method for bypassing errors is described to permit debug in the presence of multiple bugs.",

author = "Yang, {Joon Sung} and Touba, {Nur A.}",

year = "2008",

month = dec,

day = "1",

doi = "10.1109/DFT.2008.57",

language = "English",

pages = "125--133",

journal = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",

issn = "1550-5774",

note = "23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008 ; Conference date: 01-10-2008 Through 03-10-2008",

}

TY - JOUR

T1 - Enhancing silicon debug via periodic monitoring

AU - Yang, Joon Sung

AU - Touba, Nur A.

PY - 2008/12/1

Y1 - 2008/12/1

N2 - Scan-based debug methods give high observability of internal signals, however, they require halting the system to scan out responses from the circuit-under-debug (CUD). This is time consuming as many scan dumps may be required. In this paper, conventional scan chains that have non-destructive scan out capability are configured to operate as multiple MISRs during system operation. Information from the multiple MISRs is monitored periodically to identify erroneous behavior. A procedure for constructing the MISRs to maximize debug capability is described. A three step process is used to zero in on the first clock cycle in which an error is present with a small number of scan dumps. Moreover, a method for bypassing errors is described to permit debug in the presence of multiple bugs.

AB - Scan-based debug methods give high observability of internal signals, however, they require halting the system to scan out responses from the circuit-under-debug (CUD). This is time consuming as many scan dumps may be required. In this paper, conventional scan chains that have non-destructive scan out capability are configured to operate as multiple MISRs during system operation. Information from the multiple MISRs is monitored periodically to identify erroneous behavior. A procedure for constructing the MISRs to maximize debug capability is described. A three step process is used to zero in on the first clock cycle in which an error is present with a small number of scan dumps. Moreover, a method for bypassing errors is described to permit debug in the presence of multiple bugs.

UR - http://www.scopus.com/inward/record.url?scp=67649980064&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=67649980064&partnerID=8YFLogxK

U2 - 10.1109/DFT.2008.57

DO - 10.1109/DFT.2008.57

M3 - Conference article

AN - SCOPUS:67649980064

SP - 125

EP - 133

JO - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

JF - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

SN - 1550-5774

M1 - 4641165

T2 - 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008

Y2 - 1 October 2008 through 3 October 2008

ER -