Faulty cell repair with redundancy can improve memory yield. In particular, built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. We propose an efficient BIRA algorithm to achieve the optimal repair rate with a very short analysis time and low hardware cost. The proposed algorithm can significantly reduce the number of backtracks in the exhaustive search algorithm: it uses early termination based on the number of orthogonal faulty cells and fault classification in fault collection. Experimental results show that the proposed BIRA methodology can achieve optimal repair rate with low hardware overhead and short analysis time, as compared to previous BIRA methods.
|Number of pages||6|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|Publication status||Published - 2010 Jul|
Bibliographical noteFunding Information:
Manuscript received November 13, 2009; revised January 28, 2010. Date of current version June 18, 2010. The work of I. Pomeranz and S. M. Reddy was supported in part by the Semiconductor Research Corporation, under Grants 2007-TJ-1643 and 2007-TJ-1642, respectively. This paper was recommended by Associate Editor, F. Lombardi.
All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering