The gate-all-around structure is a promising candidate for future generations of advanced metal-oxide semiconductor field-effect transistor technologies, as it provides higher drive current and low-power operation. The commonly-suggested nanowire structure uses a selective etching technique in the silicon/silicon-germanium multilayer to reveal the channel area. The revealed Si surface is rough, however, due to the missing atoms and remnants of Si1-xGex. This leads to increased interfacial state density, which degrades device performance, such as subthreshold voltage swing. Regarding the usage of high-k metal gates on the channel area, the issue of this rough surface, and the subsequent increase of the dangling bonds after etching, should be properly addressed. In this study, we report the enhanced roughness and density of interface state by applying a Si capping layer. The epitaxial Si0.87Ge0.13 layer, with a thickness of 30 nm on the Si substrate, was removed by an etchant consisting of nitric acid, hydrofluoric acid, and acetic acid, after which a 1-nm thick Si capping layer was epitaxially grown onto the surface. Atomic Force Microscopy was used to measure the roughness, and X-ray Photoelectron Spectroscopy was conducted to characterize the atomic bonds on the surface. A 10-nm thick SiO2 film was deposited using the Atomic Layer Deposition process to characterize the capacitance-voltage curve and interface trap density. The Si-capped sample exhibited half of the surface roughness of the un-capped sample, and exhibited a 30% lower interface trap density, by mitigating the impact of wet etching.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Surfaces and Interfaces
- Surfaces, Coatings and Films
- Metals and Alloys
- Materials Chemistry