ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

Inayat Ullah, Joon Sung Yang, Jaeyong Chung

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


Static random access memory (SRAM)-based ternary content-addressable memory (TCAM) on field-programmable gate arrays (FPGAs) is used for packet classification in software-defined networking (SDN) and OpenFlow applications. SRAMs implementing TCAM contents constitute the major part of a TCAM design on FPGAs, which are vulnerable to soft errors. The protection of SRAM-based TCAMs against soft errors is challenging without compromising critical path delay and maintaining a high search performance. This brief presents a low-cost and low-response-time technique for the protection of SRAM-based TCAMs. This technique uses simple, single-bit parity for fault detection which has a minimal critical path overhead. This technique exploits the binary-encoded TCAM table maintained in SRAM-based TCAMs for update purposes to implement a low-response-time error-correction mechanism at low cost. The error-correction process is carried out in the background, allowing lookup operations to be performed simultaneously, thus maintaining a high search performance. The proposed technique provides protection against soft errors with a response time of 293 ns, whereas maintaining a search rate of 222 million searches per second on a 1024\times40 size TCAM on Artix-7 FPGA.

Original languageEnglish
Article number9005222
Pages (from-to)1084-1088
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number4
Publication statusPublished - 2020 Apr

Bibliographical note

Funding Information:
Researchers divide the wide TCAM bit patterns into smaller chunks as they do not scale well in terms of required memory November10,2019;acceptedDecember17,2019.Date ofpublicationManuscriptreceivedJune 27,2019;revisedSeptember14,2019 and in SRAM-based TCAMs. The W -bit wide bit patterns of TCAM February 20, 2020; date of current version March 20, 2020. This work with depth D are divided into smaller chunks of C bits and then was supported by the Samsung Research Funding and Incubation Center of implemented using AND-cascaded 2C × D size SRAMs [8], [9]. This SamsungElectronics underProjectSRFC-TB1803-02.TheEDAtoolsused is explained using a simplified implementation of an SRAM-based InayatUllahandJaeyongChungarewith theDepartmentinthisworkweresupportedbyIDEC,Daejeon,SouthKorea. TCAM shown in Fig. 1. The 4-bit patterns of a 4-word deep TCAM ics Engineering, Incheon National University, Incheon 22012, are divided into two partitions of 4 × 2, which are then implemented ( using the two 4 × 4 SRAMs shown in Fig. 1(b). Let us consider a Joon-Sung Yang is with the Department of Systems Semiconductor Engi- search key (1001) is applied for the search operation, the first two neering, Yonsei University, Seoul, South Korea (e-mail: js.yang@yonsei. bits (10) would access the third word of the first SRAM (1100) and Colorversions the last two bits (01) would access the second word of the second onlineat SRAM (1001). The SRAM words read are ANDed to get the final Digital Object Identifier 10.1109/TVLSI.2020.2968365 match result (1000) which represents a match for rule R0.

Publisher Copyright:
© 1993-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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