ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

Inayat Ullah; Joon Sung Yang; Jaeyong Chung

doi:10.1109/TVLSI.2020.2968365

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

Inayat Ullah, Joon Sung Yang, Jaeyong Chung

College of Engineering

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

Static random access memory (SRAM)-based ternary content-addressable memory (TCAM) on field-programmable gate arrays (FPGAs) is used for packet classification in software-defined networking (SDN) and OpenFlow applications. SRAMs implementing TCAM contents constitute the major part of a TCAM design on FPGAs, which are vulnerable to soft errors. The protection of SRAM-based TCAMs against soft errors is challenging without compromising critical path delay and maintaining a high search performance. This brief presents a low-cost and low-response-time technique for the protection of SRAM-based TCAMs. This technique uses simple, single-bit parity for fault detection which has a minimal critical path overhead. This technique exploits the binary-encoded TCAM table maintained in SRAM-based TCAMs for update purposes to implement a low-response-time error-correction mechanism at low cost. The error-correction process is carried out in the background, allowing lookup operations to be performed simultaneously, thus maintaining a high search performance. The proposed technique provides protection against soft errors with a response time of 293 ns, whereas maintaining a search rate of 222 million searches per second on a 1024\times40 size TCAM on Artix-7 FPGA.

Original language	English
Article number	9005222
Pages (from-to)	1084-1088
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	28
Issue number	4
DOIs	https://doi.org/10.1109/TVLSI.2020.2968365
Publication status	Published - 2020 Apr

Bibliographical note

Funding Information:
Researchers divide the wide TCAM bit patterns into smaller chunks as they do not scale well in terms of required memory November10,2019;acceptedDecember17,2019.Date ofpublicationManuscriptreceivedJune 27,2019;revisedSeptember14,2019 and in SRAM-based TCAMs. The W -bit wide bit patterns of TCAM February 20, 2020; date of current version March 20, 2020. This work with depth D are divided into smaller chunks of C bits and then was supported by the Samsung Research Funding and Incubation Center of implemented using AND-cascaded 2C × D size SRAMs [8], [9]. This SamsungElectronics underProjectSRFC-TB1803-02.TheEDAtoolsused is explained using a simplified implementation of an SRAM-based InayatUllahandJaeyongChungarewith theDepartmentinthisworkweresupportedbyIDEC,Daejeon,SouthKorea. TCAM shown in Fig. 1. The 4-bit patterns of a 4-word deep TCAM ics Engineering, Incheon National University, Incheon 22012, are divided into two partitions of 4 × 2, which are then implemented (e-mail:jychung@incheon.ac.kr). using the two 4 × 4 SRAMs shown in Fig. 1(b). Let us consider a Joon-Sung Yang is with the Department of Systems Semiconductor Engi- search key (1001) is applied for the search operation, the first two neering, Yonsei University, Seoul, South Korea (e-mail: js.yang@yonsei. bits (10) would access the third word of the first SRAM (1100) and Colorversions ofoneormoreofac.kr). the last two bits (01) would access the second word of the second onlineathttp://ieeexplore.ieee.org. SRAM (1001). The SRAM words read are ANDed to get the final Digital Object Identifier 10.1109/TVLSI.2020.2968365 match result (1000) which represents a match for rule R0.

Publisher Copyright:
© 1993-2012 IEEE.

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/TVLSI.2020.2968365

Cite this

@article{9e021ba0dcb64c2da2ca8b098ee768a6,

title = "ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs",

abstract = "Static random access memory (SRAM)-based ternary content-addressable memory (TCAM) on field-programmable gate arrays (FPGAs) is used for packet classification in software-defined networking (SDN) and OpenFlow applications. SRAMs implementing TCAM contents constitute the major part of a TCAM design on FPGAs, which are vulnerable to soft errors. The protection of SRAM-based TCAMs against soft errors is challenging without compromising critical path delay and maintaining a high search performance. This brief presents a low-cost and low-response-time technique for the protection of SRAM-based TCAMs. This technique uses simple, single-bit parity for fault detection which has a minimal critical path overhead. This technique exploits the binary-encoded TCAM table maintained in SRAM-based TCAMs for update purposes to implement a low-response-time error-correction mechanism at low cost. The error-correction process is carried out in the background, allowing lookup operations to be performed simultaneously, thus maintaining a high search performance. The proposed technique provides protection against soft errors with a response time of 293 ns, whereas maintaining a search rate of 222 million searches per second on a 1024\times40 size TCAM on Artix-7 FPGA.",

author = "Inayat Ullah and Yang, {Joon Sung} and Jaeyong Chung",

note = "Funding Information: Researchers divide the wide TCAM bit patterns into smaller chunks as they do not scale well in terms of required memory November10,2019;acceptedDecember17,2019.Date ofpublicationManuscriptreceivedJune 27,2019;revisedSeptember14,2019 and in SRAM-based TCAMs. The W -bit wide bit patterns of TCAM February 20, 2020; date of current version March 20, 2020. This work with depth D are divided into smaller chunks of C bits and then was supported by the Samsung Research Funding and Incubation Center of implemented using AND-cascaded 2C × D size SRAMs [8], [9]. This SamsungElectronics underProjectSRFC-TB1803-02.TheEDAtoolsused is explained using a simplified implementation of an SRAM-based InayatUllahandJaeyongChungarewith theDepartmentinthisworkweresupportedbyIDEC,Daejeon,SouthKorea. TCAM shown in Fig. 1. The 4-bit patterns of a 4-word deep TCAM ics Engineering, Incheon National University, Incheon 22012, are divided into two partitions of 4 × 2, which are then implemented (e-mail:jychung@incheon.ac.kr). using the two 4 × 4 SRAMs shown in Fig. 1(b). Let us consider a Joon-Sung Yang is with the Department of Systems Semiconductor Engi- search key (1001) is applied for the search operation, the first two neering, Yonsei University, Seoul, South Korea (e-mail: js.yang@yonsei. bits (10) would access the third word of the first SRAM (1100) and Colorversions ofoneormoreofac.kr). the last two bits (01) would access the second word of the second onlineathttp://ieeexplore.ieee.org. SRAM (1001). The SRAM words read are ANDed to get the final Digital Object Identifier 10.1109/TVLSI.2020.2968365 match result (1000) which represents a match for rule R0. Publisher Copyright: {\textcopyright} 1993-2012 IEEE.",

year = "2020",

month = apr,

doi = "10.1109/TVLSI.2020.2968365",

language = "English",

volume = "28",

pages = "1084--1088",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - ER-TCAM

T2 - A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

AU - Ullah, Inayat

AU - Yang, Joon Sung

AU - Chung, Jaeyong

N1 - Funding Information: Researchers divide the wide TCAM bit patterns into smaller chunks as they do not scale well in terms of required memory November10,2019;acceptedDecember17,2019.Date ofpublicationManuscriptreceivedJune 27,2019;revisedSeptember14,2019 and in SRAM-based TCAMs. The W -bit wide bit patterns of TCAM February 20, 2020; date of current version March 20, 2020. This work with depth D are divided into smaller chunks of C bits and then was supported by the Samsung Research Funding and Incubation Center of implemented using AND-cascaded 2C × D size SRAMs [8], [9]. This SamsungElectronics underProjectSRFC-TB1803-02.TheEDAtoolsused is explained using a simplified implementation of an SRAM-based InayatUllahandJaeyongChungarewith theDepartmentinthisworkweresupportedbyIDEC,Daejeon,SouthKorea. TCAM shown in Fig. 1. The 4-bit patterns of a 4-word deep TCAM ics Engineering, Incheon National University, Incheon 22012, are divided into two partitions of 4 × 2, which are then implemented (e-mail:jychung@incheon.ac.kr). using the two 4 × 4 SRAMs shown in Fig. 1(b). Let us consider a Joon-Sung Yang is with the Department of Systems Semiconductor Engi- search key (1001) is applied for the search operation, the first two neering, Yonsei University, Seoul, South Korea (e-mail: js.yang@yonsei. bits (10) would access the third word of the first SRAM (1100) and Colorversions ofoneormoreofac.kr). the last two bits (01) would access the second word of the second onlineathttp://ieeexplore.ieee.org. SRAM (1001). The SRAM words read are ANDed to get the final Digital Object Identifier 10.1109/TVLSI.2020.2968365 match result (1000) which represents a match for rule R0. Publisher Copyright: © 1993-2012 IEEE.

PY - 2020/4

Y1 - 2020/4

N2 - Static random access memory (SRAM)-based ternary content-addressable memory (TCAM) on field-programmable gate arrays (FPGAs) is used for packet classification in software-defined networking (SDN) and OpenFlow applications. SRAMs implementing TCAM contents constitute the major part of a TCAM design on FPGAs, which are vulnerable to soft errors. The protection of SRAM-based TCAMs against soft errors is challenging without compromising critical path delay and maintaining a high search performance. This brief presents a low-cost and low-response-time technique for the protection of SRAM-based TCAMs. This technique uses simple, single-bit parity for fault detection which has a minimal critical path overhead. This technique exploits the binary-encoded TCAM table maintained in SRAM-based TCAMs for update purposes to implement a low-response-time error-correction mechanism at low cost. The error-correction process is carried out in the background, allowing lookup operations to be performed simultaneously, thus maintaining a high search performance. The proposed technique provides protection against soft errors with a response time of 293 ns, whereas maintaining a search rate of 222 million searches per second on a 1024\times40 size TCAM on Artix-7 FPGA.

AB - Static random access memory (SRAM)-based ternary content-addressable memory (TCAM) on field-programmable gate arrays (FPGAs) is used for packet classification in software-defined networking (SDN) and OpenFlow applications. SRAMs implementing TCAM contents constitute the major part of a TCAM design on FPGAs, which are vulnerable to soft errors. The protection of SRAM-based TCAMs against soft errors is challenging without compromising critical path delay and maintaining a high search performance. This brief presents a low-cost and low-response-time technique for the protection of SRAM-based TCAMs. This technique uses simple, single-bit parity for fault detection which has a minimal critical path overhead. This technique exploits the binary-encoded TCAM table maintained in SRAM-based TCAMs for update purposes to implement a low-response-time error-correction mechanism at low cost. The error-correction process is carried out in the background, allowing lookup operations to be performed simultaneously, thus maintaining a high search performance. The proposed technique provides protection against soft errors with a response time of 293 ns, whereas maintaining a search rate of 222 million searches per second on a 1024\times40 size TCAM on Artix-7 FPGA.

UR - http://www.scopus.com/inward/record.url?scp=85082539221&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85082539221&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2020.2968365

DO - 10.1109/TVLSI.2020.2968365

M3 - Article

AN - SCOPUS:85082539221

SN - 1063-8210

VL - 28

SP - 1084

EP - 1088

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 4

M1 - 9005222

ER -

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this