This paper proposes to exploit the capability of retention time relaxation in flash memories for improving the lifetime of an SLC-based SSD. The main idea is that as a majority of I/O data in a typical workload do not need a retention time larger than a few days, we can have multiple partial program states in a cell and use every two states to store one-bit data at each time. Thus, we can store multiple bits in a cell (one bit at each time) without erasing it after each write-that would directly translates into lifetime enhancement. The proposed scheme is called Dense-SLC (D-SLC) flash design which improves SSD lifetime by 5.1X-8.6X.
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2 ACKNOWLEDGMENT This work is supported in part by NSF grants 1302557, 1213052, 1439021, 1302225, 1629129, 1526750, and 1629915, a grant from Intel, NRF 2016R1C1B2015312 and 2015M3C4A7065645, and MSIP IITP-2015-R0346-15-1008.
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Computer Networks and Communications