Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network

Minje Jun, Sungroh Yoon, Eui Young Chung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its topology design, since the topology largely determines its overall performance. For this purpose, they mostly require a switch library which includes all possible switch configurations (e.g. the number of in/output ports and data width) with their implementation costs such as delay, area, and power. More precisely, they characterize the switches by synthesizing them with a common design objective (e.g. minimizing area) and common design constraints for a given gate-level design library. The implementation costs are used in evaluating the topologies throughout the topology synthesis. The major drawback of single switch library approach is that it forces the topology synthesis methods to search the best topology with the assumption that all the switches comprising a topology will be implemented (synthesized) with a common design objective and common design constraints. Such assumption prevents them from exploring diverse combinations of the switches for a topology from the implementation perspective. To tackle this issue, we propose a topology synthesis method with multiple switch libraries, where the switch libraries are prepared with different design objectives and design constraints. The experimental results show that the power consumption and the area of optimal topologies can be saved by up to 67.1% and 27.2%, respectively, by the proposed method with negligible synthesis time overhead.

Original languageEnglish
Title of host publicationDATE 10 - Design, Automation and Test in Europe
Pages1390-1395
Number of pages6
Publication statusPublished - 2010 Jun 9
EventDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010 - Dresden, Germany
Duration: 2010 Mar 82010 Mar 12

Other

OtherDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010
CountryGermany
CityDresden
Period10/3/810/3/12

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Switches
Topology
Costs
Electric power utilization
Automation

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Jun, M., Yoon, S., & Chung, E. Y. (2010). Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network. In DATE 10 - Design, Automation and Test in Europe (pp. 1390-1395). [5457030]
Jun, Minje ; Yoon, Sungroh ; Chung, Eui Young. / Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network. DATE 10 - Design, Automation and Test in Europe. 2010. pp. 1390-1395
@inproceedings{5eea28da893c410cad8d99731de1967e,
title = "Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network",
abstract = "On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its topology design, since the topology largely determines its overall performance. For this purpose, they mostly require a switch library which includes all possible switch configurations (e.g. the number of in/output ports and data width) with their implementation costs such as delay, area, and power. More precisely, they characterize the switches by synthesizing them with a common design objective (e.g. minimizing area) and common design constraints for a given gate-level design library. The implementation costs are used in evaluating the topologies throughout the topology synthesis. The major drawback of single switch library approach is that it forces the topology synthesis methods to search the best topology with the assumption that all the switches comprising a topology will be implemented (synthesized) with a common design objective and common design constraints. Such assumption prevents them from exploring diverse combinations of the switches for a topology from the implementation perspective. To tackle this issue, we propose a topology synthesis method with multiple switch libraries, where the switch libraries are prepared with different design objectives and design constraints. The experimental results show that the power consumption and the area of optimal topologies can be saved by up to 67.1{\%} and 27.2{\%}, respectively, by the proposed method with negligible synthesis time overhead.",
author = "Minje Jun and Sungroh Yoon and Chung, {Eui Young}",
year = "2010",
month = "6",
day = "9",
language = "English",
isbn = "9783981080162",
pages = "1390--1395",
booktitle = "DATE 10 - Design, Automation and Test in Europe",

}

Jun, M, Yoon, S & Chung, EY 2010, Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network. in DATE 10 - Design, Automation and Test in Europe., 5457030, pp. 1390-1395, Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, Dresden, Germany, 10/3/8.

Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network. / Jun, Minje; Yoon, Sungroh; Chung, Eui Young.

DATE 10 - Design, Automation and Test in Europe. 2010. p. 1390-1395 5457030.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network

AU - Jun, Minje

AU - Yoon, Sungroh

AU - Chung, Eui Young

PY - 2010/6/9

Y1 - 2010/6/9

N2 - On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its topology design, since the topology largely determines its overall performance. For this purpose, they mostly require a switch library which includes all possible switch configurations (e.g. the number of in/output ports and data width) with their implementation costs such as delay, area, and power. More precisely, they characterize the switches by synthesizing them with a common design objective (e.g. minimizing area) and common design constraints for a given gate-level design library. The implementation costs are used in evaluating the topologies throughout the topology synthesis. The major drawback of single switch library approach is that it forces the topology synthesis methods to search the best topology with the assumption that all the switches comprising a topology will be implemented (synthesized) with a common design objective and common design constraints. Such assumption prevents them from exploring diverse combinations of the switches for a topology from the implementation perspective. To tackle this issue, we propose a topology synthesis method with multiple switch libraries, where the switch libraries are prepared with different design objectives and design constraints. The experimental results show that the power consumption and the area of optimal topologies can be saved by up to 67.1% and 27.2%, respectively, by the proposed method with negligible synthesis time overhead.

AB - On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its topology design, since the topology largely determines its overall performance. For this purpose, they mostly require a switch library which includes all possible switch configurations (e.g. the number of in/output ports and data width) with their implementation costs such as delay, area, and power. More precisely, they characterize the switches by synthesizing them with a common design objective (e.g. minimizing area) and common design constraints for a given gate-level design library. The implementation costs are used in evaluating the topologies throughout the topology synthesis. The major drawback of single switch library approach is that it forces the topology synthesis methods to search the best topology with the assumption that all the switches comprising a topology will be implemented (synthesized) with a common design objective and common design constraints. Such assumption prevents them from exploring diverse combinations of the switches for a topology from the implementation perspective. To tackle this issue, we propose a topology synthesis method with multiple switch libraries, where the switch libraries are prepared with different design objectives and design constraints. The experimental results show that the power consumption and the area of optimal topologies can be saved by up to 67.1% and 27.2%, respectively, by the proposed method with negligible synthesis time overhead.

UR - http://www.scopus.com/inward/record.url?scp=77953083702&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77953083702&partnerID=8YFLogxK

M3 - Conference contribution

SN - 9783981080162

SP - 1390

EP - 1395

BT - DATE 10 - Design, Automation and Test in Europe

ER -

Jun M, Yoon S, Chung EY. Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network. In DATE 10 - Design, Automation and Test in Europe. 2010. p. 1390-1395. 5457030