Exploring Parallel Data Access Methods in Emerging Non-Volatile Memory Systems

Myoungsoo Jung

Research output: Contribution to journalArticlepeer-review

20 Citations (Scopus)


The exploitation of internal parallelism over hundreds of NAND flash memories is becoming a key design issue in high-speed solid state disks (SSDs). In this study, we simulate a cycle-accurate SSD platform with diverse parallel data access methods and 24 page allocation strategies, which are geared toward exploiting both system-level parallelism and flash-level parallelism, using a variety of design parameters. Our extensive experimental analysis reveals that 1) the previously proposed channel striping-based page allocation strategy is not the best from a performance perspective, 2) as opposed to the common belief that system-level and flash-level concurrency mechanisms are largely orthogonal, the system-level parallel data access methods employed interferes with flash-level parallelism, 3) when most of the current currency controls and page allocation strategies are implemented, the SSD internal resources are significantly underutilized, and 4) while the performance of all the page allocation strategies on read-intensive workloads (reads > 99 percent) is improved by employing a high frequency flash interface, the performance enhancements are significantly limited. Finally, we present several optimization points to extract the maximum internal parallelism by offering comprehensive evaluations with controllable and easy-to-understand micro-benchmarks.

Original languageEnglish
Article number7514757
Pages (from-to)746-759
Number of pages14
JournalIEEE Transactions on Parallel and Distributed Systems
Issue number3
Publication statusPublished - 2017 Mar 1

Bibliographical note

Funding Information:
This work is supported by NRF grants NRF- 2016R1C1B2015312 and NRF-2015M3C4A7065645. This work is also supported in part by IT Consilience Creative Program grant IITP-2015-R0346-15-1008, DOE grant DEAC02- 05CH1123. Myoungsoo Jung has an interest in being supported for any type of engineering or costumer sample product on emerging NVM technologies (e.g., PRAM, X-Point, ReRAM, STT-MRAM etc.).

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Hardware and Architecture
  • Computational Theory and Mathematics


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